Patents Assigned to Sun Microsystems
  • Patent number: 6889343
    Abstract: In a computer system having a first repeater and a second repeater, the first repeater coupled to the second repeater by a bus, the first repeater operable to transmit a transaction and a control signal to the second repeater, a method, performed by the second repeater, of generating an error comprising: predicting, in a first cycle, that a transaction should be transmitted from the first repeater to the second repeater; determining if a control signal was received within a predetermined number of cycles of the first cycle; and if the control signal is not received within the predetermined number of cycles of the first cycle, then generating an error.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: May 3, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Tai Quan, Brian L. Smith, James C. Lewis
  • Patent number: 6889227
    Abstract: A system or method enables a two tier computer application to operate in a three tier computer environment without specific programming for the three tier environment. Such a system or method receives a database call at a computer system and maps the database call to a general programming language call of a computer application. The general programming language call is executed to invoke functions of the computer application that correspond to functions of the database call. The general programming language call may be an Enterprise Java Bean (EJB) call. An application server receives the database call and maps the database call to the general programming language call. In response to executing the general programming language call, the application server generates a second database call to the database that may either correspond directly or indirectly to the database call received at the application server. The database calls may both be SQL calls.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: May 3, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Graham Hamilton
  • Patent number: 6889329
    Abstract: The Smart Card URL Programming interface (UPI) builds a local web or card server around a card terminal and the inserted smart card. This server can also support secure object storage, which stores serialized, secure signed, compressed objects (or applications or data) for delivery to the card or for off-loading from the card. The secure object storage is also web addressable. The object storage program stores objects with the option of signing and/or encrypting and retrieves objects which may require cryptographic credentials. If a user desires to run applications on a card that exceeds the memory capacity of the card, information about the applications, including pointers and their digital signatures, is acquired and stored on the card by the card server. The card server manages the applications on a card and their movement on and off the card.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: May 3, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Rinaldo DiGiorgio, Stephen Uhler, Colin Stevens
  • Patent number: 6889248
    Abstract: A server network is described. In one embodiment, the server network comprises a global master server, a local master server and one or more slave servers. The local master server is coupled to the central master server via a first network and is synchronized to the global master server. The one or more slave servers are coupled to the local master server via a second network to perform manufacturing tasks to facilitate building products. The global master, local master and slave servers are programmed the same and configurable to different tasks, including automatically configurable as a master or server based on the interface of the server to which they are coupled.
    Type: Grant
    Filed: April 12, 2000
    Date of Patent: May 3, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Lyle Scheer
  • Patent number: 6886798
    Abstract: A support for holding an electronics assembly, comprises: (i) a rigid frame (6) that can be secured to the assembly; (ii) one or more cushioning elements (8) for protecting an electronics assembly held by the support against mechanical shocks during handling; and (iii) a plurality of handles (16) to enable the support to be manually lifted. The handles may be employed to lift both the assembly and the support, or they may be used to release the support from the assembly once the assembly is in place in an electronics cabinet. The support protects the assembly during installation in data centres after other packing materials have been discarded.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: May 3, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Matthew C. Cain, Jay Kevin Osborn, John David Schnabel, Denise Silverman, Andrew John Yair
  • Patent number: 6883716
    Abstract: Means and a method for authenticating a photographic image (3) on an identification device (1), the identification device (1) being provided with: a photographic image of a person (3) and a microprocessor (8), the microprocessor (8) having: a) a processor (7), b) a memory (9) connected to the processor (7) and having stored authentication data, and c) interface means (5) connected to the processor (7) for communicating with an external device, wherein said photographic image (3) comprises steganographically hidden information, the content of which together with said authentication data allows authentication of said photographic image (3), the method having the following steps: a?) scanning the photographic image (3) and generating image data, b?) analyzing these image data in accordance with a predetermined image analysis procedure to derive said hidden information, and c?) carrying out the authentication of the photographic image (3) based on the hidden information and the authentication data.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Eduard Karel De Jong
  • Patent number: 6886157
    Abstract: Methods, apparatus and computer program products are disclosed for a method of invoking a native method in a Java virtual machine (“JVM”). A special-purpose fast interface, executing in conjunction with an interpreter loop, for native methods reduces C stack recursion in the JVM. The interface performs as an extension to the interpreter loop component in the JVM in that a native method, invoked via the special-purpose interface, is able to modify the interpreter loop state if necessary. This is done without adding new bytecode instructions. A method of executing a native method in a Java virtual machine is described. The JVM first determines whether a native method is to be handled by a special native interface or one of multiple other native interfaces. If it is determined that the method is to be handled by the special native interface, the method is invoked and passed arguments enabling it to access the state of the JVM. The method is then executed.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Dean R. E. Long, Christopher J. Plummer, Nedim Fresko
  • Patent number: 6885361
    Abstract: An apparatus for providing a tactile stimulus to a part of the body of a physical operator when a virtual operator, created by movements of the physical operator, encounters a virtual object defined by a computer. A signalling unit communicates with the computer and emits a signal when the virtual operator encounters a virtual object. A stimulus unit responsive to the signalling unit is disposed in close proximity to a part of the body of the physical operator for providing a tactile stimulus when the virtual operator encounters a virtual object. The stimulus unit may comprise a segment of memory metal which undergoes a martensitic transformation to a different form or a solenoid having a member which moves in response to a signal emitted by the signalling unit. A vibrating member, such as a piezoceramic bender may be used instead of or in addition to the solenoid or memory metal.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Young L. Harvill, Jean-Jacques G. Grimaud, Jaron Z. Lanier
  • Patent number: 6886031
    Abstract: A method for efficient connection establishment and use for message passing on a single symmetric multiprocessor node or on a cluster of symmetric multiprocessor nodes is provided. Further, a method of memory management for message passing on a single symmetric multiprocessor node or on a cluster of symmetric multiprocessor nodes is provided. The invention utilizes dynamic memory allocation for both memory needed for messages and acknowledgment memory segments. Moreover, a method for reclaiming memory used to send a message or piece thereof is provided.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Narayan Venkatsubramanian, Terry D. Dontje, Steve Sistare
  • Patent number: 6885375
    Abstract: A method and a system for stalling large pipelined designs. A computational pipeline may comprise a first module and a second module coupled together. The first module may propagate one or more signals to the second module. A stall-signal may be asserted in order to stall the computational pipeline if the second module is not ready to receive the one or more signals from the first module. The one or more signals propagated from the first module and the asserted stall-signal may be buffered in a stall-buffer. The asserted stall-signal may be propagated to the first module in a next cycle. The first module may be stalled in response to the first module receiving the propagated asserted stall-signal. Next, the asserted stall-signal may be propagated up the computational pipeline.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Brian D. Emberling, Ewa M. Kubalska, Steve Kurihara, Anthony S. Ramirez, Andre J. Gaytan
  • Patent number: 6886081
    Abstract: A method for determining an ownership of for a multiple owner lock. The method includes determining potential owners of the lock by inspecting a core file of a computer system or memory of a live system to determine which threads have pointers to the lock. The method includes identifying a stack for the threads with a stack pointer pointing to the current active frame and dividing the stack into active and inactive portions. The stack information is examined for each potential owner of the lock for pointers to the lock. If the thread has a pointer to the lock in the inactive portion of the stack, the thread is removed from the set of potential owners. The method includes retrieving a waiting list for the lock, and any threads on the waiting list are removed from the set of potential owners.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: John M. Harres
  • Patent number: 6886053
    Abstract: Provided are a method, system, and program for selecting a path to a device to use when sending data requests to the device. Data requests are submitted to the device on a first path. Device information is maintained indicating a position of a data transfer mechanism of the device that performs the submitted data request. A second path to the device is selected if the first path fails. Data requests are submitted to the indicated position.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Stephen D. Paul
  • Patent number: 6885384
    Abstract: A system and method are disclosed for reproducing a pre-selected larger 2-D sample location pattern from a smaller one by means of X,Y address permutation. This method, for example, allows hardware to effectively reproduce a pre-selected set of sample locations for an array of 128×128 sample bins from a smaller set of pre-selected sample locations for an array of 2×2 sample bins. A permutation logic unit may use a first portion of an address for a sample bin B to identify a corresponding 2-D transformation, apply the inverse of the transformation to a second portion of the sample bin address to identify the corresponding bin of the 2×2 array of sample bins, and apply the transformation to the sample locations stored in the corresponding bin to reproduce the sample locations pre-selected for sample bin B.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael F. Deering, Nathaniel David Naegle, Ranjit S. Oberoi
  • Patent number: 6885610
    Abstract: A system and method for adjusting the clock delay in a self-timed memory system having a memory array and a sense amplifier includes a programmable delay circuit coupled as an input to the sense amplifier for controlling the timing of when the sense amplifier is enabled in relation to the memory array addressing by generating a plurality of delayed versions of the sense amplifier enable signal and coupling one of the delayed versions of the sense amplifier enable signal to the sense amplifier in response to a control signal. By multiplexing multiple delayed versions of the sense amplifier enable signal under control of programmable delay selection logic, an optional delay is provided to make enable the sense amplifier more quickly or more slowly in reference to a memory array signal, depending upon control signal inputs to the selection logic.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Toshinari Takayanagi
  • Patent number: 6886145
    Abstract: A testbench for an integrated circuit (IC) design including a chain of scan circuits having a memory characteristic is verified by: (a) dividing the chain of scan circuits and creating a plurality of partitions, each partition including at least one logic cone output, each scan circuit belonging to one of the partition as a logic cone output; (b) generating a partitioned netlist for each partition from a full netlist for the IC design, the partitioned netlist including at least one logic cone, the logic cone extending from the logic cone output to at least one logic cone input; (c) generating a partitioned testbench for each partition from the full testbench based on the partitioned netlists; and (d) performing verification for the testbench by simulating the partitioned testbenches on the corresponding partitioned netlists.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Scott Davidson, Ramesh C. Tekumalla
  • Patent number: 6886108
    Abstract: A storage device is monitored for data integrity errors and each detected data integrity error is stored in a count. When that count reaches a threshold limit, the storage device is placed into a forced failure state.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Nisha D. Talagala
  • Patent number: 6882354
    Abstract: A graphical user interface uses scroll bars having a single pixel width and a much larger scroll button or thumb. Both the scroll bar and the scroll button may be controlled to have selective degrees of transparency so that they underlying image information may be seen under certain conditions. In one application, the scroll bar itself is invisible until a cursor approaches to within a specified proximity. The graphical user interface permit scroll bars to be displayed which follow an arbitrary path in either two or three dimensions.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: April 19, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Jakob Nielsen
  • Patent number: 6883010
    Abstract: One embodiment of the present invention provides a system for elevating a secondary file server to act as a new primary file server in a highly available file system. Upon determining that a primary file server in the highly available file system has failed, the system promotes the secondary file server to become the new primary file server. During this process, the new primary file server scans file objects to look for a file lock indication. Upon finding a file lock indication, the new primary file server converts an associated file identifier into a virtual node. Otherwise, conversion of file identifiers into virtual nodes is delayed until the first time a file is subsequently accessed by the new primary server, thereby speeding up the failover process.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: April 19, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Michael J. Byrne
  • Patent number: 6882645
    Abstract: One embodiment of the present invention provides a system that facilitates implementing a memory mechanism within an asynchronous switch fabric. The system includes a memory device, which does not preserve first-in, first-out semantics such as a random access memory or a stack. The system also includes a data destination horn, for routing data from a trunk line to a plurality of destinations. The memory device is one destination of the plurality of destinations. The system further includes a data source funnel, for routing data from a plurality of sources into the trunk line. The memory device is a source of the plurality of sources.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: April 19, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Ian W. Jones
  • Patent number: D504425
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: April 26, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Nigel D. Ritson, Paul J. Garnett