Abstract: A method and apparatus for installing distributed objects on a distributed object system is described. In one aspect the distributed objects include wrapper classes that inherit object attributes through an inheritance relationship with a developer-written servant class of objects, the developer-written servant classes inheriting attributes through an optional inheritance relationship with an interface class of objects. In a preferred embodiment, the wrapper classes provide an interface mechanism between the methods of the servant class of objects and the object request broker mechanism of the distributed object system. Also included is an apparatus for creating and installing the distributed object in the memory of a computer on a distributed object system. The invention further includes a mechanism for distinguishing deployed distributed objects from development distributed objects.

Abstract: The health of a process is monitored in a computer system by a process monitor. The monitored process (a configuration management system daemon (CMSD)) is not a child of the process monitor. The process monitor uniquely determines the identity of a monitored process and verifies the correct operation of the monitored process. In the absence of verification of the correct operation of the monitored process, the monitored process is caused to initiate. On successful initiation of the monitored process, the monitored process is uniquely identified to the system and is detached from the process monitor. Each monitored process is arranged to write, on initiation, its unique process identification information (PID) to a file, which file is then accessed by the process monitor to identify the process monitor. The process monitor can interrogate the operating system to verify correct operation of the CMSD.

Abstract: A method for reducing voltage variation in the power supply system of a phase locked loop has been developed. The method includes powering up a phase locked loop and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the phase locked loop, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: In an embodiment, an apparatus for enhancing a thermal match between portions of a semiconductor device is disclosed. The apparatus includes a die and a heat spreader. The heat spreader is in thermal contact with the die. The heat spreader has a center portion and a perimeter portion. The center portion and the perimeter portions are structurally coupled to each other. In another embodiment, the perimeter portion of the heat spreader is selected from material with a lower CTE than the material for the center portion of the heat spreader.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A field and/or customer replaceable packaged refrigeration heat sink module is suitable for use in standard electronic component environments. The field replaceable packaged refrigeration heat sink module is self-contained and is specifically designed to have physical dimensions similar to those of a standard air-based cooling system, such as a fined heat sink or heat pipe. As a result, the field replaceable packaged refrigeration heat sink module can be utilized in existing electronic systems without the need for board or cabinet/rack modification or the “plumbing” associated with prior art liquid-based cooling systems.

Abstract: A system for managing cables is disclosed herein. A preferred aspect of the system comprises a flat panel monitor having a front surface, a rear surface, a left side surface and a right side surface. The system also comprises a plurality of downwardly facing cable portals coupled to the rear surface of the flat panel monitor and a stand coupled to the rear surface of the flat panel monitor, wherein the flat panel monitor is forwardly rotatable on said the on a horizontal axis; and a plurality of releasably connectable retaining member are coupled to the rear surface of the flat panel monitor.

Abstract: An integrated circuit is presented having a plurality of logic modules dispersed about a surface of a semiconductor substrate. Each logic module includes a set of control and status registers including at least one control register storing a control value. A functional unit of each logic module performs one or more logic functions dependent upon the control value stored in the control register. A central controller is coupled to the each of the logic modules. The central controller is adapted to receive address, data, and control signals (e.g., from signal lines of an external bus coupled to I/O pads of the integrated circuit), and issues read/write commands to read/write the control and status registers dependent upon the address, data, and control signals. A write command may, for example, modify the control value stored in a selected one of the control registers. The integrated circuit may include a bus which couples the central controller to each of the logic modules.

Abstract: A system and method for efficient layout of a display table. Given a description of a table, such as a markup language description, the table description may be parsed and data structures representing the table description may be created. The table description data structures may then be “inspected”, in order to determine the possible size of the table. Once the table has been inspected, the table may then be “apportioned”, based on the results of the inspection step. That is, final dimensions may be assigned to the table. The table coordinates may then be “normalized”, which may involve converting relative table coordinates into absolute coordinates. Table layout optimizations are described, e.g., in order to efficiently handle various aspects of table layout, such as table cells that span multiple columns or rows, table cells that include nested tables, etc.

Abstract: A computer system is described including a processor for executing instructions, a memory module for storing instructions and data, and a memory controller coupled between the processor and the memory module. The memory controller provides a differential clock signal and memory access signals which are routed to the memory module. The memory module includes multiple memory devices coupled to a clock buffer. The clock buffer produces a new single-ended “regenerated” clock signal from the differential clock signal. The clock buffer includes an input buffer circuit and a phase-locked loop (PLL). The input buffer circuit receives the differential clock signal from the memory controller and produces a single-ended reference clock signal from the differential clock signal. The PLL produces the regenerated clock signal substantially at the same frequency of, and in synchronization with, the single-ended reference clock signal produced by the input buffer circuit.

Abstract: A decoupling capacitor assignment technique that increases decoupling capacitance without violating a leakage power constraint of an integrated circuit is provided. The decoupling capacitor assignment technique selectively replaces decoupling capacitors associated with high driver decoupling capacitance need to available decoupling capacitance ratios with thin-oxide decoupling capacitors such that decoupling capacitance is increased and the leakage power constraint is met.

Abstract: A memory architecture in accordance with an embodiment of the present invention improves the speed of method invocation. Specifically, method frames of method calls are stored in two different memory circuits. The first memory circuit stores the execution environment of each method call, and the second memory circuit stores parameters, variables or operands of the method calls. In one embodiment the execution environment includes a return program counter, a return frame, a return constant pool, a current method vector, and a current monitor address. In some embodiments, the memory circuits are stacks; therefore, the stack management unit to cache can be used to cache either or both memory circuits. The stack management unit can include a stack cache to accelerate data transfers between a stack-based computing system and the stacks. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit.

Abstract: A method and structure for supply gating low power electronic components uses low threshold gating transistors. The low power components operate at supply voltages of less than one volt and typically in the range of 150 to 400 millivolts. Using low threshold gating transistors, the leakage current of the devices, and therefore the standby power dissipation, can be minimized by using any one, or a combination of, four methods including: overdriving the low threshold gating transistors on; overdriving the low threshold gating transistors off; combining very low threshold device transistors with low threshold gating transistors; and providing the low threshold gating transistors with back bias.

Abstract: Post-manufacture variation of timing may be employed to address data-dependent degradation or creep in device characteristics affecting a differential circuit. One particular example of such data-dependent degradation or creep involves Negative Bias Temperature Instability (NBTI). In certain memory circuit configurations, NBTI can cause threshold voltage (Vt) of PMOS devices to increase by an amount that depends on the historical amount of voltage bias that has been applied across gate and source/drain nodes. In the case of many sense amplifier designs, a predominant value read out using the sense amp may tend to disparately affect one device (or set of devices) as compared with an opposing device (or set of devices). In other words, if the same data value is read over and over again, then one of two opposing PMOS devices of a typical sense amp will accumulate an NBTI-related Vt shift, while the opposing PMOS device will accumulate little or no shift.

Abstract: Methods, systems, and articles of manufacture provide configuration data from a configuration server to a client. The configuration server receives a request to provide a value for a configuration data item. The configuration server then determines a set to which the configuration item is assigned, with the set being associated with a rule. Then, the configuration server determines a value of the configuration item by applying the rule associated with the set and transmits the determined value of the configuration item to the client.

Abstract: A method for updating Enterprise JavaBeans (EJB) classes is provided. Each EJB class is managed by an application server which maintains a database of active EJB classes. The method includes defining an update plug for an existing EJB class and assigning the update plug to the existing EJB. The method also includes compiling the existing EJB class using the update plug to generate a dependent EJB class. The dependent EJB class uses an adapter and a contract to gain access to methods of the dependent EJB class. Each method of the dependent EJB class is associated with an algorithm that defines a locking timestamp.

Abstract: A method and system for storing instructions retrieved from memory in a memory cache to provide said instructions to a processor. First a new instruction is received from the memory. The system then determines whether the new instruction is a start of a basic block of instructions. If the new instruction is the start of a basic block of instructions, the system determines whether the basic block of instructions is stored in the memory cache responsive. If the basic block of instructions is not stored in the memory cache, the system retrieves the basic block of instructions for the new instruction from the memory. The system then stores the basic block of instructions in a buffer. The system then predicts a next basic block of instructions needed by the processor from the basic block of instructions.

Abstract: A method for datum sharing between modular computer system components, includes determining a position and orientation of a motherboard, defining at least one datum feature in a primary chassis describing the position and orientation of the motherboard, and defining at least one datum feature in a secondary chassis corresponding to the at least one datum feature in the primary chassis. An apparatus for datum sharing includes at least one datum feature of the primary chassis, at least one datum feature of the motherboard, wherein a location of the at least one datum feature of the primary chassis is based upon the at least one datum feature of the motherboard, and at least one datum feature of the secondary chassis, wherein a location of the at least one datum feature of the secondary chassis is based upon the location of the at least one datum feature of the primary chassis.

Abstract: A method and system is provided for delaying the loading of classes that are unnecessary the start-up of an applet when a server sends an applet to a client. Methods and systems consistent with the present invention package the class files necessary for start-up of the applet on the client in a single archive file along with relatively small interface classes that reference the delayed classes This archive file, being smaller, saves download time and can be sent with a single connection from the server computer to the client computer, as opposed to multiple connections. These methods and systems consistent with the present invention also provide a way for the client computer to request the delayed classes not included in the initial archive file if the delayed class is later needed by the client computer.

Abstract: One or more embodiments of the invention provide Common Desktop Environment (CDE) applications with the ability to utilize JavaBeans components and applications written in the Java programming language. Such an embodiment provides for the use of a virtual machine that maintains the ability to execute and return results from applications written in the Java programming language. Similarly, one or more embodiments of the invention provide applications written in the Java programming language with the ability to utilize CDE applications. In one or more such embodiments, a module (referred to as a CDEBean) launches a generic application to perform the datatyping and launch of CDE applications. Since a CDEBean is a JavaBeans component, the use of a CDE application is transparent to the application itself. Consequently, one or more embodiments provide for the transparent use of CDE applications in an application written in the Java programming language.