Abstract: A method of operating a computer system includes providing a program in memory, verifying the program prior to an installation of the program and generating a program fault signal when the verification fails. The program includes at least one program unit, and each program unit includes an Application Programming Interface (API) definition file and an implementation. Each API definition file defines items in its associated program unit that are made accessible to one or more other program units and each implementation includes executable code corresponding to the API definition file. The executable code includes type specific instructions and data. Verification includes determining whether a first program unit implementation is internally consistent, determining whether the first program unit implementation is consistent with a first program unit API definition file associated with the first program unit implementation and generating a program fault signal when the verifying fails.

Abstract: A caching pattern and associated method for caching in a programming environment are disclosed. The caching pattern includes an extensible cache entry component that includes methods for retrieving, updating, and setting expiration parameters for a cache entry. A cache store component includes methods for reading and writing objects to cache entries. A cache manager component includes methods implementing a first interface to the cache store component to cause the cache store component to read and write objects to the data store and includes methods implementing a second interface to the cache entry component for adding, removing, getting and committing data to the cache entry. The cache store component may also include instantiating a virtual machine and the caching pattern may be used, in one embodiment, in a JAVA programming environment.

Abstract: A network and storage I/O device is described for use with a host computer system having a system bus coupled to a host processor and a main memory to provide a high bandwidth network server system. The network and storage I/O device includes a plurality of network controllers to communicate with client computers connected over a network, a plurality of storage controllers to transfer data to and from storage devices, at least one memory element to temporarily store data transferred between the network controllers and the storage controllers and a crossbar switch having a plurality of nodes to interconnect the plurality of network controllers, the plurality of storage controllers and the at least one memory element. The network and storage I/O device also includes a bridge coupled between one of the nodes and the system bus of the host computer.

Abstract: In accordance with the present invention, a method is described which facilitates heat transfer from a silicon die after the silicon die is bonded to a substrate. An alignment tool is used to align the spacer with the silicon die. A thermal conductor can be placed on the silicon layer after the silicon layer has been bonded to the substrate layer. A die interface material is not necessarily applied between the silicon die and the thermal conductor. A spacer is used between the substrate and the thermal conductor. The spacer can facilitate heat transfer from the die. The spacer can facilitate force transfer from the thermal lid to the die. The spacer allows a thermal conductor to be affixed to the silicon die without use of a die interface. An alignment tool is used to align the spacer with the silicon die.

Abstract: The present invention discloses a method and device for placing prefetch instruction in a low-level or assembly code instruction stream. It involves the use of a new concept called a martyr memory operation. When inserting prefetch instructions in a code stream, some instructions will still miss the cache because in some circumstances a prefetch cannot be added at all, or cannot be added early enough to allow the needed reference to be in cache before being referenced by an executing instruction. A subset of these instructions are identified using a new method and designated as martyr memory operations. Once identified, other memory operations that would also have been cache misses can “hide” behind the martyr memory operation and complete their prefetches while the processor, of necessity, waits for the martyr memory operation instruction to complete. This will increase the number of cache hits.

Abstract: The present invention provides a method and apparatus for replacing a filter. The apparatus includes a receptacle adapted to receive a filter that is capable of filtering a first area. The apparatus further includes at least one supporting member to support at least a portion of the filter and at least a portion of a replacement filter, wherein both the filter and replacement filter are adapted to filter at least a portion of the first area for a selected duration.

Abstract: A technique for maintaining referential integrity between data records in any data architecture in which only a single copy is kept of any particular data record. The technique includes providing the ability to bind a data record to a parent data record by storing the data record in a manner associated with the parent record. If the data record then is bound to other parent data records, a link reference is used that is stored in an attribute of the data record, rather than associating another copy of the data record with the second parent data record. It is possible to bind any data record to any other data record, so circular relationships can be created. In addition, there are special methods used when a data record is to be deleted to make sure that all parents or children of that data record are considered, in order to update bind information or delete the children as may be appropriate.

Abstract: Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.

Abstract: A computer system includes a register that is configured to contain a zero value. In response to a predetermined occurrence on the computer system, such as a hardware interrupt, the computer system launches a trap routine. This routine generates output data that needs to be stored within the memory space of the computer system. In order to write out this data from within the trap routine, a desired target address is specified as a negative offset from the zero value stored in the register. This avoids the need to have to locate another (unused) register in which to store the write address.

Abstract: A method for automatically maintaining a database that stores coverage data for testing software code under development is provided. The method includes providing modified instrumented software and using test cases of a test suite to execute the modified instrumented software. Modified coverage data that includes a call tree defining a path of each test case is created. The method also includes replacing the coverage data with the modified coverage data at scheduled intervals.

Abstract: An intelligent test system for testing software code is provided. The intelligent system includes a profiled software component, a test executor, a database, a database updater, and a data analyzer/optimizer. The test executor creates a coverage data by using the profiled software component to execute a plurality of test cases of a test suite. The database stores the coverage data and the database updater is configured to store the coverage data into the database. The data analyzer/optimizer analyzes the coverage data contained in the database to find test cases affected by a modification to the software code. The data analyzer/optimizer also optimizes the test cases affected by the modification by selecting fewer test cases that satisfy a criteria. The test executor uses the test cases that satisfy the criteria to test the modification to the software code.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: One embodiment of the present invention provides a system for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information. The system receives a circuit divided into modules coupled together by a number of signal lines. The system defines a first set of timing constraints, and uses the first set of timing constraints to compile the circuit from a hardware description language specification into a first gate-level implementation. Next, the system performs a timing analysis on the first gate-level implementation to determine positive or negative slack values for the signal lines. These slack values specify amounts of extra propagation delay available on the signal lines. Next, the slack values are used to define a second set of timing constraints by allocating the slack values between the modules based upon wireload information.

Abstract: A technique for reducing the power consumed by a clock driver circuit involves selecting between a first power supply path and a second power supply path in response to a power reduction signal. A driver circuit drives an output clock signal from the selected one of the first power supply path and the second power supply path. By reducing the voltage on one of the first power supply path and the second power supply path, the power consumed by the clock driver circuit may be selectively reduced.

Abstract: A dynamic circuit capable of operating in a normal power consumption mode and at least one reduced power consumption mode is provided. The dynamic circuit is operatively connected to a normal supply voltage and a reduced supply voltage, and is capable of operating at either the normal supply voltage and a normal frequency or at the reduced supply voltage and a reduced frequency. By using such a dynamic circuit, power consumption may be selectively controlled in order to reduce unnecessary power consumption.

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

Abstract: In accordance with methods and systems consistent with the present invention, a system that automatically generates Fortran 90 interfaces to Fortran 77 code is provided. These interfaces provide for the use of optional parameters and, because they are written in Fortran 90, also allow for parameter checking. These interfaces are automatically generated to allow a programmer to reap the benefits of Fortran 90 calling without having to rewrite the Fortran 77 underlying code. When generating the interfaces, the method performs an optimization that saves a significant amount of processing time as well as a significant amount of memory. This optimization involves generating the interfaces in such a way as to prevent the compiler from performing a gather and a scatter.

Abstract: A computer bus rack includes at least one circuit board. The circuit board has an increased density of add-on card slots, with the at least one circuit board having a front side and a back side, and the rack comprising a first plurality of slots coupled to the front side, and a second plurality of slots coupled to the back side. The first and second plurality of slots are arranged such that corresponding ones of the first and second slots are in substantial alignment, respectively. Also provided are a plurality of connectors having respective connector-pins extended in a direction substantially perpendicular to and away from the circuit board and having a column and row arrangement within the connectors. The connectors are affixed to the circuit board in alignment with the first and second plurality of slots, and each one of the plurality of connectors has connector-pins that are physically distinct from connector-pins of connectors of the other slots.

Abstract: An address decoder having pre-decode logic circuitry positioned in between ends of final decode logic circuitry is provided. Such an address decoder yields less wire load, less gate load, less power consumption, and increased speed due to the pre-decode logic circuitry having to be capable of only driving a signal over half the length of a final decoder. Further, a method to select memory elements from a memory array using centrally positioned pre-decode logic circuitry is provided.

Abstract: CSMA/CD is used to implement flow control in a full-duplex Ethernet network in a lossless fashion. Uniquely identifiable flow control transmit on/off (“XON/XOFF”) messages are transmitted, preferably during IPG, by a receiving station about to be congested to the transmitting station whose data output is to be controlled. The transmitting station physical layer receives and decodes these messages. If XOFF is recognized, the transmitting station continuously asserts CRS to its MAC layer at the MII, regardless of the prior CRS current state. CRS is continuously asserted until the receiving station transmits an XON flow control signal, indicating its ability to accept further data. During CRS assertion, the transmitting station defers transmission, e.g., is flow controlled.