Abstract: Provided are a computer implemented method, system, and program for enabling access to information from a device. A device program is generated to access device property information from the device. Each device property indicates a state of the device and the device program includes device specific commands to query the device for information on the device properties and device independent statements common to device programs for other devices to buffer the queried property information to return to requesting clients. The device program is stored in a computer readable medium.

Abstract: A system and method of installing a software patch on a selected electronic device using a graphical user interface is disclosed. The user utilizes a graphical user interface (GUI) to select a patch to install and selects an electronic device, the “target” device, upon which to install the patch. Patch dependencies on the target device are programmatically determined and checked to ensure that software required for the patch is present on the target device. The installation of the patch is then performed. The illustrative embodiment of the present invention also enables the removal of a patch from a targeted device following a determination of which applications on the target device are dependant upon the patch, and subsequent user authorization of the removal operation.

Abstract: The present invention provides an interactive graphical user interface (GUI) patch environment for installing a patch on the targeted systems. A system administrator or other authorized user interfaced with a machine may perform the installation of a patch on the machine using a software wizard. Additionally, the Wizard pre-verifies the patch dependencies (pre-installed software) required by the patch and checks the target systems to ensure the target systems possess the requisite dependencies. Once the target systems have been validated and the required dependencies identified on the target systems, the sequencing algorithm sorts patches in correct order before applying patches to the target systems. The user can remove the patch from the pre-validated patch list about to be applied to the target system. The patch dependency is checked before removing the patch from the pre-validated patch list for proper removal order.

Abstract: A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.

Abstract: A bit line that has a feedback path from the bit line to a storage cell on the bit line is provided. The feedback path allows the bit line to discharge through a discharge device that is connected to a non-discharging local bit line. Further, a discharge device capable of discharging a global bit line even when a storage cell connected to the discharge device is not being evaluated is provided. Further, a method to perform a memory array operation by discharging a bit line using multiple discharge devices is provided.

Abstract: Disclosed are novel methods and apparatus for efficiently providing critical path analysis of a design. In an embodiment, an apparatus disclosed can assist in creating a single critical path schematic which can be used to simulate both rising and falling edge delays. This saves time as only one schematic and one simulation is required instead of the two generally required.

Abstract: A method and apparatus for adaptably providing data to a virtual desktop system is described. The computational service provider is configured to prepare and transmit one or more data streams through a viable interconnection fabric to multiple HIDs. The data stream is configured by the computational service provider to adaptably meet the performance needs of the HID receiving the data stream. This enables multiple HIDs to receive variants of the same data stream that may differ in quantity, quality, and/or data format. In one embodiment of the invention, a decode module prepares data for transport by separating decoded data into individual processes. Before a HID may connect to a process the HID is authenticated. The processes are further adjusted by a resource optimization module to take into account the characteristics of each HID requesting access.

Abstract: Region based optimization may be accomplished by creating dependence graphs for each block and then incrementally computing a single dependence graph for the region. First dependence DAGs are created for each block in the region. This includes defining incoming and outgoing dangling edges for each block. Each dependence DAG is then linked as a control flow graph. Examining of each incoming dangling edge within each block of the region then takes place, with the process traversing each path along the control flow graph in reverse, attempting to match each incoming dangling edge with a corresponding incoming or outgoing dangling edge, stopping only if an outgoing match is found, the same block is examined twice, or the top of the region is found.

Abstract: An integrated circuit that asymmetrically shields a signal to increase decoupling capacitance is provided. The signal is asymmetrically shielded based on a probability of the signal being at a specific value. Further, a computer system that uses asymmetrically shielding to increase performance is provided. Further, a method for increasing an amount of implicit decoupling capacitance on a circuit through asymmetric shielding is provided. Further, a method to increase component performance by increasing implicit decoupling capacitance is provided.

Abstract: A method and apparatus for providing plug-in media decoders. Embodiments provide a “plug-in” decoder architecture that allows software decoders to be transparently downloaded, along with media data. User applications are able to support new media types as long as the corresponding plug-in decoder is available with the media data. Persistent storage requirements are decreased because the downloaded decoder is transient, existing in application memory for the duration of execution of the user application. The architecture also supports use of plug-in decoders already installed in the user computer. One embodiment is implemented with object-based class files executed in a virtual machine to form a media application. A media data type is determined from incoming media data, and used to generate a class name for a corresponding codec (coder-decoder) object.

Abstract: In accordance with the present invention, a method is described which facilitates heat transfer from a silicon die after the silicon die is bonded to a substrate. The thermal conductor is placed on the silicon layer after the silicon layer has been bonded to the substrate layer. A spacer is used between the substrate and the thermal conductor. The spacer can facilitate heat transfer from the die. The spacer facilitates force transfer from the thermal conductor to the die. In an embodiment, the thermal conductor can be removed and a second thermal conductor used to further facilitate heat transfer. In an enablement, a heat sink and heat sink interface are provided and further facilitate heat transfer from the package. The specification also teaches an integrated circuit package manufactured by the method taught. The specification also teaches a computer system including an integrated circuit package manufactured by the method taught.

Abstract: Methods and apparatus for enabling document access across a firewall are disclosed. A method of accessing a document across a firewall includes obtaining a document access request on the first side of the firewall, where the document access request specifies a document control command and an associated file name. The document access request is then packaged in at least one client e-mail. The client e-mail is then sent across the firewall to the second side of the firewall. One or more acknowledgement e-mails are then received across the firewall from the second side of the firewall, where the acknowledgement e-mails specify a status of the executed document control command. In addition, a method of providing access to a document across a firewall includes receiving a client e-mail across the firewall from the first side of the firewall, where the client e-mail includes a document access request specifying a document control command and an associated file name.

Abstract: Method and system for lossless compression coding of a digitally represented image. The image is expressed as one or more blocks, each block having a sequence of pixels with binary pixel values. Within each block, a predictor index is chosen that predicts a pixel value as a linear combination of adjacent (actual) pixel values. The predicted and actual values are compared, and twice the predicted value is compared with the sum of the actual value and a maximum predicted value, to determine a value index, which is used to represent each pixel value in a block in compressed format. Use of the value index representation reduces the average number of bits needed to express each pixel value by an estimated 33-46 percent, reduces the time required for compression encoding by an estimated 4-6 percent, and reduces the time required for decompression by an estimated 49-61 percent.

Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.

Abstract: Method and system for compression coding of a digitally represented video image. The video image is expressed as one or more data blocks in two or more frames, each block having a sequence of pixels with pixel values. Within each block of a frame, an intra-frame predictor index or inter-frame predictor index is chosen that predicts a pixel value as a linear combination of actual pixel values, drawn from one frame or from two or more adjacent frames. The predicted and actual pixel values are compared, and twice the predicted value is compared with the sum of the actual value and a maximum predicted value, to determine a value index, which is used to represent each pixel value in a block in compressed format in each frame. The compression ratios achieved by this coding approach compare favorably with, and may improve upon, the compression achieved by other compression methods.

Abstract: The middle of line segments may be drawn on a computer display using an iterative method that reduces the number of calculations required. The process is repeated for each column. The first pixel is plotted according to a formula that allows the first pixel to best represent the location of the line in the column. A second pixel is then plotted either above, below, to the left of, or the right of the first pixel depending on the direction of the line. A normalized intensity value between 0 and 1.0 is then assigned to the first pixel according to the amount of area above, below, to the left of, or the right of the line in the first pixel depending on the direction of the line. This value may be assigned using a variable computed in plotting the first pixel. A normalized intensity value for the second pixel equal to 1.0 minus the normalized intensity value of the first pixel may then be assigned. Finally, the first and second pixels are shaded according to the normalized intensity values.

Abstract: An electromagnetic interference (EMI) shield fills an aperture in a wall of a system unit housing. The electromagnetic interference shield is integrally formed from sheet metal (e.g. stainless steel). It comprises a perforated substantially planar portion with fingers defined around the periphery thereof. A plurality of first fingers are preformed to define abutments to abut against an outer surface of the wall and a plurality of second fingers are preformed to define sprung latches for latching within the aperture. The combination of first and second fingers means that the EMI shield can be located in the aperture in a removable manner without the use of tools. The perforations are configured to permit ventilation of the interior system housing while preventing EMI interference radiating from the system housing. A handle portion is also formed at the periphery of the substantially planar portion for facilitating the insertion and removal of the shield.

Abstract: A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copied to local memory space of a node such that accesses to the data may be performed locally rather than globally. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, multiple pages of the address space are mapped to an entry in a translation table. To decrease the probability that an entry is not available for a page, the translation table may be implemented as a skewed-associative cache that implements an insertion algorithm that realigns the translations in the table to maximize the utilization of the available entries is implemented.

Abstract: Method and system for providing a netlist driven integrated router in a non-netlist driven environment for microprocessor designs includes retrieving top level netlist for the existing microprocessor design from the top level database and the design parameters for the new microprocessor design, and translating these netlist and design parameters at the front end so that the resulting data can be provided to an integrated router which is configured to generate re-routes for the new microprocessor design based on the top level netlist and the design parameters, where the generated re-routes are provided to a back end for translating the re-routes to new top level netlist and merging the new top level netlist with the existing top level netlist database.

Abstract: An optimized system and method for a parallel leading zero anticipation which ascertains “end of run” patterns in parallel. A string representing the operands of the floating-point addition is divided into nibbles of predetermined bit length (normally 4 bits). Each nibble is analyzed for the end of run patterns and the results from this analysis determine whether a run of leading zero's or one's has ended within the nibble, and if there has been an end of run, the location (bit) of the end of run. The highest order nibble that has an end of run provides the higher order bits in the LZA (leading zero anticipator output) value, while the lower two bits of the LZA value are correlated from the location end of run within the nibble, as previously determined.