Abstract: One embodiment of a transfer node is described, including a first channel port adapted for coupling to a host computer, a second channel port adapted for coupling to a storage controller and one or more storage devices, a central processing unit (CPU) coupled to the first and second channel ports, and a memory coupled to the CPU. The transfer node receives data routing information associated with a data transfer command from the storage controller via the second channel port, wherein the data transfer command directs a transfer of data between the host computer and the one or more storage devices. The transfer node stores the data routing information within the memory, and routes data associated with the data transfer command between the first and second channel ports using the data routing information stored within the memory.

Abstract: A data visualization arrangement for facilitating the display of data items comprising a selected region of an object in a selected one of a plurality of display modes. The arrangement comprises a data object store, an interface, an object region retrieval component and a display. The data object store stores the data object, the data object comprising a plurality of data items in a predetermined organization. The interface receives a region identification for identifying a particular region of the object and a display mode identification. The object region retrieval component retrieves data items from a region of the data object as identified by the region identification received by the interface. Finally, the display receives the data items as retrieved by the object region retrieval mechanism and displays them in the display mode as identified by the display mode identification.

Abstract: Executing a thread unaware or non-thread-safe application in a multi-threaded environment is potentially hazardous. If multiple instances of the thread unaware application are executed concurrently in the same process space, as may be the case in a multi-threaded environment, one instance may try to modify or overwrite the information used by the other instance, which can lead to serious errors. To enable a thread unaware application to be executed safely in a multi-threaded environment, multiple thread pools are implemented. That is, for each thread-unaware or non-thread-safe application, a separate thread pool is defined and associated with the application. Unlike other thread pools, though, this thread pool has its maximum number of threads parameter set to “1”. By limiting the number of threads in the pool to 1, it is guaranteed that there will be no more than one instance of the thread unaware application executing at any one time.

Abstract: A technique for verifying on-chip decoupling capacitance using transistor and capacitor surface area information is provided. The technique broadly includes determining a surface area of a transistor, determining a surface area of a decoupling capacitor, comparing the surface area of the transistor to the surface area of the decoupling capacitor to obtain a surface area ratio, and verifying whether there is enough decoupling capacitance based on the surface area ratio. Further, the present invention also provides a technique for determining when and how to redesign a microprocessor in order to have sufficient decoupling capacitance.

Abstract: In accordance with methods and systems consistent with the present invention, an improved technique for reconfiguring networks is provided. By using this technique, a network administrator can reconfigure their network while it remains operational. As a result, users can continue to utilize the network during reconfiguration. Additionally, in accordance with methods and systems consistent with the present invention, a number of network topologies are provided that are designed to facilitate reconfiguration. When using one of these topologies, the network can be reconfigured with a minimal amount of recabling, thus reducing the amount of time required for reconfiguration.

Abstract: A system and method for compression of surface normals in three-dimensional graphics data. The method comprises compressing a normal by identifying the location of a first point located at the intersection of the surface of a predetermined sphere (centered on the origin of a set of x-y-z axes) and a vector extended from the origin in a direction specified by the coordinate values of the normal. Identification of the first point includes specifying an index value and one or mapping values. The index value is usable during decompression to identify a second point on the sphere from a plurality of points in a predetermined surface region (such as a predetermined sextant of a predetermined octant region). In one embodiment, the index includes a &thgr; component and a &phgr; component which are usable to locate the second point.

Abstract: A computer cooling system including a cooling fluid source, and a cooling duct array adapted to distribute cooling fluid from the cooling fluid source over a plurality of high dissipation components on a circuit board.

Abstract: A proxy server operative to accept plug-in filters to perform forward and reverse filtering between a client process and a server process. In accordance with one aspect of the invention, a method of filtering information includes the steps of receiving a request by the proxy server from a client. The proxy server identifies a Uniform Resource Locator (URL) of a server process in the request and compares that URL against filter rules previously defined to the system. In the event the URL satisfies one of the filter rules, a filter servlet associated with the satisfied filter rule is used to filter the requested information. A filter servlet is a set of instructions that, when executed, filters the information. The filtered request is then used to retrieve information from a server process. Similarly, the same filtering process may be performed on a response from the server process destined for a client process.

Abstract: A capture device for use with circuit boards of varying thicknesses prevents the spacing between the boards from increasing and has a unitary body including a flexible arm, a clip cavity and multiple living hinges that enable the device to be pivotally self-locked between the circuit boards. The capture device can be engaged and disengaged in poor visibility and limited access areas densely packed with circuit boards. The capture device may be made of a semi-rigid material that provides enough flexibility for the living hinges, yet is rigid enough to exert pressure on the boards and prevent the spacing between the boards from increasing. In alternative embodiments, more than two circuit boards may be secured using alternative configurations of the capture device with either multiple arms or multiple clip cavities.

Abstract: A method of automatically performing a component test at any number of locations in a distributed environment is disclosed. In general, in order to assure compatibility of the various components in an enterprise computing system, a service test is created as part of a compatibility test suite and passed to a test application server having a test application program. The test application program includes a generic vehicle class that includes a plurality of vehicle class invokers each of which is used to implement each of the object types that are run in each of a plurality of containers. During the build process of the CTS, each service test is automatically packaged with each of the appropriate vehicle classes so that each can be deployed into and run within the associated container.

Abstract: Various methods and systems for handling and directing wireless packet data traffic is disclosed. In one embodiment, the system is a data switching system that includes a first data port interface coupled to a first data communication port, a second data port interface coupled to a second data communication port, and a data packet parsing engine responsive to the first data port interface and the second data port interface. The data packet parsing engine includes a wireless data packet evaluation routine to retrieve and evaluate content contained within the wireless data packet. In another embodiment, a method of processing wireless data traffic is provided. The method includes receiving the wireless data traffic at a gateway, evaluating a data packet within the wireless data traffic at the gateway to determine at least one of language information, user browser type information, and data content type information, and sending a data request to a particular computer server.

Abstract: A dynamic sequential device is provided that is adapted for scan control and observation. The dynamic sequential device may be scanned in-circuit as part of a scan chain in a VLSI device or it may be scanned as a discrete device. The dynamic sequential device maintains performance with respect to speed while allowing control and observation of its internal machine states.

Abstract: A trace scheduler schedules instructions within a trace and after register allocation. The trace scheduler computes critical path information across the trace, which is used to schedule instructions across basic block boundaries. In this manner, the efficiency of the compiler is maximized.

Abstract: Modified full-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. Consequently, the modified full-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.

Abstract: A system and method is provided for scan control and observation of a logical circuit that does not halt the operation of the system clock. Thus, all dynamic circuits within the system continue to evaluate and precharge normally. Moreover, the traditional method of placing a multiplexer before the data input of a clocked storage element to perform scan control and observation is no longer required. Consequently, the system and method provide a more efficient manner in which to perform scan control and observation of a logical circuit.

Abstract: A system for selecting routing information from a routing table describing alternative routes between end nodes. The routing table represents a set of minimum cost, deadlock-free routes between end nodes. The selected routing information is included in forwarding tables, and sent to networking devices in the network. The selected routing information is optimized for at least one network performance metric, such as overall network capacity or fault tolerance. Capacity optimization is obtained by selecting from alternative routes stored within the routing table such that the standard deviation of the number of routes flowing over each link in the network is minimized. Fault tolerance optimization is achieved by selecting from the alternative routes stored in the routing table such that the selected route for a given end node pair has a “failover” route with a maximum number of dissimilar links from the selected route.

Abstract: A routing graph (e.g., a 2.5-D graph) and a method for generating same is provided for more efficient multiple-layer path searching and routing. Subgraphs are generated for each layer, and then are combined (e.g., through via connections) into a single, multi-layer graph. The resulting 2.5-dimensional graph may be used in VLSI routing, for example, which commonly includes multiple routing layers in a given design space. Each subgraph corresponds to a layer of circuitry and includes segments based on segments from other layers and intersection points of all such segments.

Abstract: Modified full-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. Consequently, the modified full-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.

Abstract: Provided are a method, system, and program for generating an installation package for an application. The application is intended to execute on an operating system of an end user computer. A translator program installed on the end user computer converts code in the application to native operating system commands. Provided are the application and a launcher program including code to perform operations on an end user computer including the operating system to launch the application. A launcher application including code to call the launcher program is accessed.

Abstract: Provided are a method, system, program, and data structure for implementing a locking mechanism to control access to a shared resource. A request is received to access the shared resource. A determination is made of whether a first file has a first name. The first file is renamed to a second name if the first file has the first name. A second file is updated to indicate the received request in a queue of requests to the shared resource if the first file is renamed to the second name. An ordering of the requests in the queue is used to determine whether access to the shared resource is granted to the request. The first file is renamed to the first name after the second file is updated.