Abstract: An apparatus and method for interfacing with a metrics database is provided for getting metrics data and grouping metrics data in response to a query. The metrics database interface gets metrics data by retrieving a set of metrics data from the metrics database in response to a query and determining a set of unique tags. The metrics database interface also groups a set of metrics data in response to a query so that the group can be referenced in a subsequent query.
Abstract: Solutions to a value recycling problem that we define herein facilitate implementations of computer programs that may execute as multithreaded computations in multiprocessor computers, as well as implementations of related shared data structures. Some exploitations of the techniques described herein allow non-blocking, shared data structures to be implemented using standard dynamic allocation mechanisms (such as malloc and free). A class of general solutions to value recycling is described in the context of an illustration we call the Repeat Offender Problem (ROP), including illustrative Application Program Interfaces (APIs) defined in terms of the ROP terminology. Furthermore, specific solutions, implementations and algorithm, including a Pass-The-Buck (PTB) implementation are also described. Solutions to the proposed value recycling problem have a variety of uses.
Type:
Application
Filed:
January 10, 2003
Publication date:
July 24, 2003
Applicant:
Sun Microsystems, Inc.
Inventors:
Mark S. Moir, Victor Luchangco, Maurice Herlihy
Abstract: A method and apparatus for managing how threads of a multi-threaded computer program share a resource is provided One thread of the program is given priority over other threads of the program by granting to the thread possession of the lock associated with the resource regardless of whether the thread currently requires use of the resource. The other threads are designed to indicate to the priority thread when they require use of the resource. If the priority thread is done using the resource and detects that another thread is waiting to use the resource, the priority thread releases the resource lock for the resource. After releasing the lock for the resource, the priority thread automatically requests the resource lock. After using the resource, any non-priority thread releases the resource lock to the priority thread if the priority thread has requested the resource, without regard to whether any other threads may be waiting for the resource.
Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key which is used to compile software to be executed on the CPU. When a program is compiled for the CPU, the program is modified in order that execution may be performed with the CPU having its operation modified to accommodate the encrypted format of the software. Logic architecture is able to shift the basic op code execution function, and the logic circuitry permits modifying operation of the microprocessor in accordance with logic instruction op codes stored in distributed memory locations. This logic circuitry is configurable in accordance with the received logic instructions during the execution of a program, and it is unnecessary to decrypt the program into standard op codes prior to execution.
Abstract: Systems consistent with the present invention a method and apparatus is provided for selectively supplying a state change associated with remote objects in a distributed system. The method involves registering a request from a computational entity to receive notification as to a state change associated with a remote object. Registration of a notification request causes the creation of a remote weak reference to the remote object including an identifier of a location of the remote object. Periodically, a request is sent to a location based on the identifier of the remote weak reference. When it is determined that a state change associated with the remote object has occurred, the registered computational entity is notified accordingly.
Abstract: A technique Readjusting a bias-generator in a delay locked loop after fabrication of the delay locked loop. The technique involves use of an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated.
Type:
Grant
Filed:
April 24, 2002
Date of Patent:
July 22, 2003
Assignee:
Sun Microsystems, Inc.
Inventors:
Claude Gauthier, Brian Amick, Dean Liu, Pradeep Trivedi
Abstract: Methods and apparatus for implementing a core application programming interface which is a part of more than one application programming interface are disclosed. According to one aspect of the present invention, a class structure in an object based system is arranged to provide application programming interfaces which enable access to a system database. The class structure includes a first set of classes that define a core application programming interface, a second set of classes that define a client application programming interface, and a third set of classes that define a server application programming interface. The second set of classes includes the first set of classes, and the third set of classes includes the second set of classes. In one embodiment, the first set of classes includes interfaces.
Type:
Grant
Filed:
May 14, 1998
Date of Patent:
July 22, 2003
Assignee:
Sun Microsystems, Inc.
Inventors:
Jeffrey A. Schmidt, Bernard A. Traversat, Thomas Saulpaugh, Gregory L. Slaughter
Abstract: A system and method are provided for efficient handling of streaming-data in a cache memory system having a cache controller and at least one cache with a number of cache-lines, each cache-line including at least one way capable of caching data. In the method a request to cache data is received in cache controller (140), it is determined from the request whether the data is streaming-data and the data is cached. Optionally, cache-line (160) includes data-store (165) in which the data is cached and tag-field (175) in which information about the data is stored, and the method further includes the step of setting streaming-data-bit (200) in the tag-field to identify the data as streaming-data. In one embodiment, determining whether the data is streaming-data involves recognizing a special instruction to cache streaming-data in a request from a processor (110) executing a program or from a compiler compiling a program.
Abstract: A delay locked loop design that uses a switch operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a switch in series with the loop filter capacitor, the leakage current of the loop filter capacitor may be controlled by switching the switch ‘on’ when a charge pump of the delay locked loop is ‘on’ and switching the switch ‘off’ when the charge pump is ‘off,’ thereby cumulatively reducing the leakage current of the loop filter capacitor throughput the operation of the delay locked loop. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable delay locked loop behavior.
Type:
Grant
Filed:
July 19, 2002
Date of Patent:
July 22, 2003
Assignee:
Sun Microsystems, Inc.
Inventors:
Pradeep Trivedi, Claude R. Gauthier, Dean Liu
Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design.
In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.
Type:
Grant
Filed:
March 4, 2002
Date of Patent:
July 22, 2003
Assignee:
Sun Microsystems, Inc.
Inventors:
Xuejun Yuan, Xiaowei Jin, Rambabu Pyapali, Raymond A. Heald, James M. Kaku, Helen Dunn, Thelma C. Taylor, Peter F. Lai, Aharon Ostrer
Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.
Type:
Grant
Filed:
February 25, 2000
Date of Patent:
July 22, 2003
Assignee:
Sun Microsystems, Inc.
Inventors:
William C. Van Loo, Satyanarayana Nishtala
Abstract: A power converter within an integrated circuit (“IC”) for providing DC power to one or more function circuit, where the power converter has a transformer circuit for receiving an AC power signal and for supplying a transformed AC power signal. A converter circuit receives the transformed AC power signal and then converts the signal into a DC power signal supplied to one or more function circuit. The transformed AC power signal might either be stepped up or stepped down. The transformer circuit might comprise two coils, where a first coil is magnetically coupled to a second coil. The first coil is a first spiral and the second coil is a second spiral wherein an insulating material layer is disposed between the first spiral and the second spiral. The transformer circuit might include transformers connected in parallel or in series and may further be connected correspondingly to more than one converter circuit coupled in parallel.
Abstract: A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.
Abstract: A method and system for compiling a grammatical form of an object-oriented database into an intermediate form of that database. The grammatical form is a persistent form of an object-oriented database expressed in a human-readable and human-editable textual form according to a grammar. The textual form is parsed into a series of tokens. The tokens are compiled into a plurality of entries. The plurality of entries are expressed in an intermediate form. The intermediate form comprises an array of intelligent entry objects which encapsulate data with methods for manipulating that data. The methods include creating a database entry, creating a property associated with an entry, creating an attribute associated with an entry or property, querying the last entry, property, or attribute created, and finalizing entry storage. The intermediate form lacks the infrastructure of the database, but the intermediate form can be used to populate the object-oriented database with entries.
Type:
Grant
Filed:
February 19, 1999
Date of Patent:
July 22, 2003
Assignee:
Sun Microsystems, Inc.
Inventors:
Thomas E. Saulpaugh, Gregory L. Slaughter, Bernard A. Traversat
Abstract: A carry-out bit generator determines if a bit pattern from two positive numbers matches one of the patterns for which a carry-out bit would be generated in addition. These patterns include a TnG pattern and a Tm pattern (with a carry-in). Superscript n represents a number between zero and m−1, superscript m represents the number of registers, T represents a 0/1 or 1/0 pair and G represents a 1/1 pair.
Abstract: Methods and systems for accessing information in and loading encrypted information to memory. A processor provides virtual address information to a memory management unit. In response, the memory management unit retrieves a key tag and physical address information corresponding to the virtual address information. The memory management unit then sends the key tag and physical address information to the processor. The processor then determines whether a memory location corresponding to the physical address information is encrypted based on the key tag, and retrieves a secret key using the key tag based on the determining. Thereafter, information read from the memory location is decrypted using the secret key.
Abstract: A program interpreter for computer programs written in a bytecode language, which uses a restricted set of data type specific bytecodes. The interpreter, prior to executing any bytecode program, executes a bytecode program verifier procedure that verifies the integrity of a specified program by identifying any bytecode instruction that would process data of the wrong type for such a bytecode and any bytecode instruction sequences in the specified program that would cause underflow or overflow of the operand stack. If the program verifier finds any instructions that violate predefined stack usage and data type usage restrictions, execution of the program by the interpreter is prevented. After pre-processing of the program by the verifier, if no program faults were found, the interpreter executes the program without performing operand stack overflow and underflow checks and without performing data type checks on operands stored in operand stack. As a result, program execution speed is greatly improved.
Abstract: Provided are a method, system, and program for managing a configuration file including device parameters that define attributes of at least one device. A device driver uses the device parameters to control the at least one device. A determination is made of device parameters provided with the device driver for a device, wherein the device parameters are maintained external to the configuration file. User selection of at least one of the determined device parameters is received and a parameter code for each selected device parameter is written to the configuration file.
Type:
Application
Filed:
January 16, 2002
Publication date:
July 17, 2003
Applicant:
Sun Microsystems, Inc.
Inventors:
William L. Duncan, Ian F. Reeve, Karl A. Sutterfield
Abstract: Techniques for online upgrading of software components are disclosed. The techniques are especially suited for online upgrading of container-based software components in object oriented computing environments. A multi-stage online upgrade system can facilitate online installation of the container-based software components (e.g., applications) in object oriented computing environments. Moreover, online software upgrades can be achieved without interrupting online services which are provided by the container-based software components. The multi-stage online upgrade system can be implemented so as to allow interaction with an upgrade management entity (e.g., an application developer or system administrator). This allows controlling and/or monitoring of the online upgrade operations.