Abstract: Circuitry including a request queue and a bad address handling circuit. The request queue includes an entry for each outstanding load requesting access to a cache. Each request queue entry includes a valid bit, an issue bit and a flush bit. The state of the valid bit indicates whether or not the associated access request should be issued to the cache. The issue bit indicates whether the load access request has been issued to the cache and the flush bit indicates whether the data retrieved from the cache in response to the request should be loaded into a specified register. The bad address handling circuit responds to a replay load request by manipulating the states of the valid or flush bit of the relevant request queue entry to prevent completion of bad consumer load requests. The bad address handling circuit includes a validation circuit and a flush circuit.

Abstract: A computer graphics system that utilizes a super-sampled sample buffer and a programmable sample-to-pixel calculation unit for refreshing the display, wherein the graphics system may adjust filtering to reduce artifacts or implement display effects. In one embodiment, the graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders a plurality of samples and stores them into a sample buffer. The sample-to-pixel calculation unit reads the samples from the super-sampled sample buffer and filters or convolves the samples into respective output pixels which are then provided to refresh the display. The sample-to-pixel calculation unit may selectively adjust the filtering of stored samples to reduce artifacts, e.g., is operable to selectively adjust the filtering of stored samples in neighboring frames to reduce artifacts between the neighboring frames.

Abstract: A computer-implemented method and apparatus in a computer system for inter-process communication. A first procedure allocates a first buffer in a first memory space shared by the first procedure (e.g. a client process) and a second procedure (e.g. a kernel or server process). The first procedure then marshals arguments for communicating with the second procedure in the first buffer. The first procedure indicates that a message for the second procedure is being passed and passes a first reference to the first buffer in the first memory space to the second procedure. The second procedure detects the indication of the message by the first procedure. The second procedure then references the first buffer and copies the arguments contained in the first buffer into a temporary buffer. The second procedure can then deallocate the first buffer.

Abstract: A method for extracting parasitic capacitance from an integrated circuit layout includes decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions. The method further includes summing capacitances between the conductive segments in a selected net and the other conductive segments in the integrated circuit layout that are aligned with the conductive segments in the selected net and multiplying the sum by a first scaling factor to obtain a first capacitance value. The method further includes summing capacitances between the conductive segments in the selected net and the other conductive segments in the integrated circuit layout that are transverse to the conductive segments in the selected net to obtain a second capacitance value. The first capacitance value and the second capacitance value are added together to obtain a total capacitance value for the selected net.

Abstract: A method and graphics system configured to perform real-time morphing of three-dimensional (3D) objects that have been compressed into one or more streams of 3D graphics data using geometry compression techniques. In one embodiment, the graphics system has one or more decompression units, each configured to receive and decompress the graphics data. The decompression units are configured to convey the decompressed data corresponding to the morphs to a graphics processor that is configured to apply weighting factors to the graphics data. The weighted results are combined to yield a morphed object that is rendered to generate one or more frames of a morphing sequence. The weighting factors may be adjusted and reapplied to yield additional frames for the morphing sequence. A method for encoding 3D graphics data to allow morphing decompression is also disclosed.

Abstract: A method of detecting congestion in a computer network uses a receiving station which determines a first number of messages missing in a first acknowledgment window. The station then determines a second number of messages missing in a subsequent acknowledgement window. The station then measures congestion on the network in response to an increase in the number of missing messages as indicated by the first number of missing messages in the first acknowledgement window and the second number of missing messages in the second acknowledgement window.

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res.

Abstract: A method for compressing 3D geometry data that is capable of compressing both regularly tiled and irregularly tiled surfaces is disclosed. In one embodiment, the method comprises examining 3D geometry data to detect the presence of regularly tiled surface portions. The 3D geometry data is then compressed by: (1) encoding any regularly tiled surface portion using a first encoding method, and (2) encoding any irregularly tiled surface portions using a second encoding method, wherein the second encoding method is different from the first encoding method. The first encoding method may encode the regularly tiled surface portions as vertex rasters, while the second method may encode the irregularly tiled surface portions by geometry compression using a generalized triangle mesh.

Abstract: A carriage, provided with a mounting for one or more media devices is slideably mountable in a system unit (for example a computer system unit) such that the carriage may be slid out of an aperture the system unit. The slideable carriage means that the system unit does not need to be opened in order to insert, remove, or replace a media drive. For example, a media drive can be removed from the system unit by sliding the carriage out of the system unit, disconnecting cables from the media drive and the removing the media drive from the carriage. Similarly, a media drive can be installed in the system unit by mounting the media drive in the carriage, connecting cables to the media drive and reinserting the carriage within the system unit. The use of the slideable carriage is particularly useful for rack mountable systems where it is undesirable to have to remove the system unit from the racking system to insert a media drive.

Abstract: A method of processing data in a system including an utility, includes the steps of starting a session, selecting a file on a local drive or by URL, wherein the file includes a name of a business object, uploading the file including the name of a business object to a server, storing data of the file in a database of the utility, performing asynchronous data processing, and downloading and saving a report after the data processing is completed.

Abstract: A system and method for upgrading software application is disclosed. The system provides a profile upgrade utility that generates a profile of desired application upgrades based upon information provided from a user. In operation, a user may provide a description of modules for upgrade, along with any associated components and a description of the module location. Using this information, the system generates a profile of the desired upgrade. The upgrade profile is then converted to a text file and uploaded to an import/export utility that retrieves the requested upgrades.

Abstract: A system for automatically encrypting and decrypting data packet sent from a source host to a destination host across a public internetwork. A tunnelling bridge is positioned at each network, and intercepts all packets transmitted to or from its associated network. The tunnelling bridge includes tables indicated pairs of hosts or pairs of networks between which packets should be encrypted. When a packet is transmitted from a first host, the tunnelling bridge of that host's network intercepts the packet, and determines from its header information whether packets from that host that are directed to the specified destination host should be encrypted; or, alternatively, whether packets from the source host's network that are directed to the destination host's network should be encrypted.

Abstract: Methods and apparatus for detecting and reporting memory leaks associated with an operating system are disclosed. In accordance with one aspect of the present invention, a method for identifying a section of dynamically allocated memory which may not be explicitly freed includes processing information associated with a failure of an operating system and identifying a call-site that is associated with the section of the dynamically allocated memory using the information. Once the call-site is identified, a report may be generated to identify the call-site as being associated with the section of dynamically allocated memory. In one embodiment, obtaining information associated with a failure of the operating system includes obtaining an image of the operating system which is created when a kernel associated with the operating system crashes.

Abstract: A method for significantly decreasing the number of times prior art coding schemes, such as variable length coding, are implemented in the course of encoding/decoding a given data block includes cataloging the occurrences, or locations, of a designated frequently occurring value in the data block and then excluding the frequently occurring value from the prior art coding scheme.

Abstract: A memory module with offset notches for improved insertion and a memory module connector for mating thereto. The connector housing includes an accommodating s space for receiving a portion of the memory module printed circuit board (PCB). A first key is disposed within the accommodating space of the housing and is positioned between the first end and the center of the housing. A second key is flirter disposed within the accommodating space and is positioned between the second end of the housing and the center. A distance between the first key and the second key is greater than 40% of the length of the housing. Either the first, second, or both keys may extend from the accommodating space beyond a top plane defined by a top side of the accommodating space of the housing. The memory module comprises the PCB with a first notch positioned between the first end of the PCB and the center of the PCB. A second notch is positioned between the second end of the PCB and the center of the PCB.

Abstract: A method for selecting a candidate to mark as overwritable in the event of a cache miss while attempting to avoid a write back operation. The method includes associating a set of data with the cache access request, each datum of the set is associated with a way, then choosing an invalid way among the set. Where no invalid ways exist among the set, the next step is determining a way that is not most recently used among the set. Next, the method determines whether a shared resource is crowded. When the shared resource is not crowded, the not most recently used way is chosen as the candidate. Where the shared resource is crowded, the next step is to determine whether the not most recently used way differs from an associated source in the memory and where the not most recently used way is the same as an associated source in the memory, the not most recently used way is chosen as the candidate.

Abstract: A method for assigning power and ground pins in array packages in order to enhance next level routing is provided. In one embodiment, the method comprises arranging connections of a semiconductor array package, the semiconductor package having an integrated circuit with power, ground, and signal connections, in 2×3 connection grids. Each connection grid includes a power connection and a ground connection which is adjacent to the power connection. The 2×3 connection grids are arranged so that each connection at the periphery is a signal connection. A 4:1:1 signal:power:ground connection ratio is maintained in the arrangement, wherein no more than four signal connections are present for each power connection, and no more than four signal connections are present for each ground connection.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: An AC sequencer receives source AC voltage via a sequence-mounted universally accepted connector, such as an IEC 309 compatible connector. Source AC is coupled by an AC connector plug and AC power cord from a wall socket to the AC sequencer via a mating connector. Although specifications for the AC power cord and AC connector will vary from country to country, the same AC sequencer may be used in many countries. Further, the AC sequencer receives control and status signals via sequencer-mounted universally accepted connectors, and can respond to signals that may be voltage-sourced, current-sourced, in addition to signals representing switch openings and closures. This permits a master server AC sequencer to be intelligently daisy-chained to remote slave units containing a similar AC sequencer, such that status information may be received from and control signals sent to the slave unit.