Abstract: Methods and apparatus for facilitating a global safepoint operation in a multithreaded computer system are disclosed. According to one aspect of the present invention, each thread keeps track of its safepoint regions by maintaining a variable which indicates a state, such as whether the current region of the thread is safe, unsafe, or transitional. In this manner, it can be determined whether a thread is currently in a safepoint region without suspending the thread. When a thread is currently in a safepoint region, the thread can continue to operate while a global safepoint operation, such as garbage-collection is being performed. When the thread begins to transition out of the safe region, it moves into a transitional region. The transitional region automatically blocks the transition into the non-safe region to assure that the safepoint operation occurs in a safe region.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).

Abstract: A microprocessor includes multiple register files. In a single thread mode, the microprocessor allows a single thread to have access to multiple ones of the register files. In a multi-thread mode, each thread has access to respective ones of the register files. In the multi-thread mode, multiple threads are simultaneously executing. Circuitry and hardware are provided to facilitate the respective modes and to facilitate transitions between the modes.

Abstract: Using a subtraction without borrow operation, the first operand lowest order word is subtracted from a second operand lowest order word. If the result of the subtracting is not zero, then a zero (Z) flag is cleared such that a Z flag status is not set. If, however, the result of the subtracting is zero, then the Z flag is set as usual. Next, a first operand next higher order word is subtracted from a second operand next higher order word using a subtraction with borrow and a sticky not Z flag (SBBZ) instruction and, based upon the subtracting, the Z flag is updated accordingly such that it represents the result of the whole multi-word subtraction until the first operand highest order word is subtracted from the second operand highest order word. The comparing of the first operand and the second operand is then based upon the Z flag status, if needed, after the subtraction of the first operand highest order word is subtracted from the second operand highest order word.

Abstract: Provided is a method, system, and program for managing multiple resources in a system. A user request is received to generate a configuration policy. User selection is received of a set of the multiple resources. A determination is made of at least one element for each selected resource in the set, wherein each element is capable of managing one of the resources in the system. User selection is received of one element for each selected resource in the set. The configuration policy is defined to include the user selected elements, wherein invoking the configuration policy further invokes each element defined in the configuration policy to configure the resources associated with the invoked elements.

Abstract: Provided is a method, system, and program for managing multiple resources in a system. A user request for an operation is received that requires performing separate element operations with respect to multiple resources in the system. In response to the user request, commands are communicated to multiple elements, wherein each element is capable of managing one of the resources in the system. For each element receiving at least one of the communicated commands, the element interprets the received commands and performs the element operation requested by the received command with respect to the managed resource. All the element operations performed by all the elements in response to receiving the commands implements the user requested operation.

Abstract: A bezel assembly for a computer enclosure includes a bezel and a hinge capable of hingedly joining the bezel to the computer enclosure. A computer system includes an enclosure, a bezel, and a hinge capable of hingedly joining the bezel to the enclosure. A method of replacing a first component with a second component in a computer system enclosure having a hinged bezel includes pivoting the hinged bezel away from the computer system enclosure and removing the first component from the computer system enclosure. The method further includes inserting the second component into the computer system enclosure and pivoting the hinged bezel toward the computer system such that the hinged bezel is adjacent the computer system enclosure.

Abstract: A method and apparatus for building an integrated circuit. A description of the logical operation of a module in a hardware description language is provided, which includes annotations in the form of design directives. An interpreting process is configured to read the annotations and identify which logical and physical design tools are needed to process each module in the description, as well as the order in which to invoke the logical physical design tools. Dependencies in the execution of the design tools on the various modules of the description are analyzed to determine where the processing of modules may be performed in parallel to optimize execution.

Abstract: A system and method for improving the isolation and diagnosis of hardware faults in a computing system wherein means are provided for indicating whether unusable data has previously triggered diagnosis of the hardware fault that caused the data to be unusable. If diagnosis has not been performed, the flag is not set. If diagnosis has already been performed, the flag is set. One embodiment comprises an interface which is used to convey data from one subsystem to another. When the interface receives data from the first subsystem, the data is examined to determine whether it contains an uncorrectable error (including missing data.) If the data contains an uncorrectable error, the interface examines the flag corresponding to the data to determine whether hardware fault diagnosis has already been initiated. If diagnosis has already been initiated, the data is passed to the second subsystem without initiating further diagnosis.

Abstract: A method and apparatus for encoding characteristics for the retrieval of information. Depending on the characteristics, some methods for retrieving information may be preferred. If information is too large to utilize UDP, then TCP may be preferred. In addition, if information is not cacheable, then it is preferable to retrieve the information directly from the server instead of searching the cache first. A URL (Uniform Resource Locator) is utilized on the internet to specify the application protocol (e.g., http), the domain name (e.g., www.sun.com), and file location (e.g., /users/hcn/index.html). The suffix of a file indicator is utilized to identify how to process the data or information subsequent to retrieval. One or more embodiments of the invention provide for encoding characteristics of data to be transferred that indicates or hints at an optimal method to retrieve the data. For example, the URL may specify that TCP is the preferred transfer protocol, thereby avoiding an attempted transfer using UDP.

Abstract: Advertising displays such as found in mass transit vehicles or stations or in electronic newspapers are provided with user directed search capabilities. Selected text, dragged and dropped onto an image space, serves to initiate a query. If the advertising display is networked, an external search of network resources, such as those of the World Wide Web, can be undertaken and the results utilized to initiate one or more local searches.

Abstract: A system for limiting security attacks on a computer system that operate by executing computer instructions embedded in data received from an external source. The system receives the data from the external source and performs a transformation on the data that causes any computer instructions encoded in the data to be unexecutable. After the data is transformed, the system stores the data in the computer system's memory. When the data is needed, the system retrieves the data and reverses the transformation. In this way, data from an external source is stored in memory in an unexecutable form, thereby making it impossible to execute malicious code embedded in the data. According to one aspect of the present invention, the data is transformed using a random number, so that the data can only be converted back to its original form with an inverse transformation using the same random number.

Abstract: A method and system for leasing storage locations in a distributed processing system is provided. Consistent with this method and system, a client requests access to storage locations for a period of time (lease period) from a server, such as the file system manager. Responsive to this request, the server invokes a lease period algorithm, which considers various factors to determine a lease period during which time the client may access the storage locations. After a lease is granted, the server sends an object to the client that advises the client of the lease period and that provides the client with behavior to modify the lease, like canceling the lease or renewing the lease. The server supports concurrent leases, exact leases, and leases for various types of access. After all leases to a storage location expire, the server reclaims the storage location.

Abstract: A method and circuitry for pre-emphasizing transmitted logic signals. The method and circuitry may be applied to single-ended center-taped terminated I/O lines. In one embodiment, a driver circuit may be configured for monitoring the logic values (i.e. logic 0, logic 1, or logic low, logic high) of signals transmitted by the driver circuit. The driver circuit may compare the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal may occur based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value may be pre-emphasized.

Abstract: In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: One embodiment of the present invention provides a system for defining signal timing for an integrated circuit device. The system operates by first creating a virtual timing reference plane for the integrated circuit device. A first signal line is then routed from a semiconductor die within the integrated circuit package to a first external connection of the integrated circuit package. Next, the system generates a first escape pattern for a first circuit trace on a printed circuit board from the first external connection to the virtual timing reference plane. This first escape pattern specifies a route from where the first external connection meets the printed circuit board to the virtual timing reference plane. Finally, the system establishes a first set of signal timings for a combination of the first signal line and the first circuit trace at the virtual timing reference plane.

Abstract: Improved techniques for representation of objects in a Java programming environment are disclosed. The techniques are highly suitable for representation of Java objects inside virtual machines, especially those that operate with limited resources (e.g., embedded systems. A cluster of Java object representations is disclosed. Each of the Java object representations provide a reference to a Java object and a reference to the class associated with the Java object. Accordingly, a two-tier representation is provided which allows efficient implementation of applications which need to access information regarding both Java objects and classes. This means that the processing required to perform applications such as garbage collection is reduced. In addition, one of the references in the two-tier representation can be implemented to provide direct access to the internal class representation associated with the object. As a result, quick access to information regarding Java objects can be achieved.

Abstract: Techniques for implementation of Java heaps are disclosed. The techniques can be implemented in a Java virtual machine operating in a Java computing environment. A Java heap potion comprising two or more designated portions is disclosed. Each of the designated heap portions can be designated to store only a particular Java logical component (e.g., Java objects, Java class representation, native components, etc.) A designated heap portion can be implemented as a memory pool. In other words, two or more designated heap portions can collectively represent a memory pool designated for a particular Java logical component. The memory pools allow for dynamic management of the designated heap portions. As a result, the performance of the virtual machines, especially those operating with relatively limited resources is improved.

Abstract: Elements on a network are selectively unmanaged by a network manager. An element is not managed when it is placed in a Pending state. Traps and events from the element in the Pending state are handled but not processed. The element can be automatically placed in the Pending state if a trap or event has been generated by that element.