Abstract: A network adapter includes a bypass buffer with sufficient capacity to store a packet from an upstream neighboring adapter and to store at least one additional incoming packet as a local packet is sent. The adapter also includes control logic which monitors the bypass buffer to determine whether the adapter may send local data packets. A network may be formed of such network adapters linked through counterrotating rings. If the control logic determines that the bypass buffer has sufficient storage available to avoid overflow while the adapter sends the local packet, the adapter sends the local packet. The control logic may choose to send a local packet only if there is sufficient room available within the bypass buffer to store a packet the same size as the local packet which is to be sent, thereby insuring that the bypass buffer does not overflow before the adapter can resume transmitting data from the bypass buffer.

Abstract: A method and apparatus for pre-processing and packaging class files. Embodiments remove duplicate information elements from a set of class files to reduce the size of individual class files and to prevent redundant resolution of the information elements. Memory allocation requirements are determined in advance for the set of classes as a whole to reduce the complexity of memory allocation when the set of classes are loaded. The class files are stored in a single package for efficient storage, transfer and processing as a unit. In an embodiment, a pre-processor examines each class file in a set of class files to locate duplicate information in the form of redundant constants contained in a constant pool. The duplicate constant is placed in a separate shared table, and all occurrences of the constant are removed from the respective constant pools of the individual class files.

Abstract: A method and apparatus for stretching and/or shortening a clock cycle uses a multiplexor stage, in which a multiplexor switches between a normal clock signal and a delayed clock signal. Further, a method and apparatus for generating a plurality of stretched and/or shortened clock cycles uses a multiplexor stage in which a multiplexor successively switches between a normal clock signal and a plurality of delayed clock signals. Further, a method and apparatus for removing a clock cycle uses a multiplexor stage, in which a multiplexor switches between either a normal clock signal or a delayed clock signal and a grounded signal.

Abstract: An operating system call control subsystem is disclosed for use in a computer that includes a processor for processing a program, the program instructions of an operating system call instruction type identifying one of a plurality of types of operating system calls, each type of operating system call being associable with an operating system call type identifier value within a predetermined range of values. The operating system call control subsystem comprises a crossover table, an operating system call instruction type address resolution module, and an operating system call instruction type processing module. The crossover table has a number of entries corresponding to a predetermined fraction of the predetermined range, each entry in the crossover table having an instruction for enabling the processor to save a value corresponding to an offset of the entry into the crossover table.

Abstract: A power supply is provided. The power supply is comprised of a first power module, a second power module, and a controller. The first power module is capable of delivering a first preselected amount of power. The second power module is capable of delivering a second preselected amount of power. The first and second power modules are coupled together to be capable of delivering an aggregate amount of power related to the first and second preselected amounts of power. The controller is adapted to selectively enable the first and second power modules to make power available in one of the first preselected amount, the second preselected amount, and the aggregate amount.

Abstract: A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header.

Abstract: A garbage collector collects a train-managed heap in accordance with the train algorithm. In doing so, it concentrates into a respective train the heap-located objects that belong to garbage cycles even if those cycles additionally include certain types of objects that are outside the train-managed heap. It does so by using objects within the heap as proxies for those extra-heap objects, and it evacuates into a proxy object's train any collection-set objects referred to by the extra-heap objects for which the proxy object is a proxy. The objects in those garbage cycles containing the extra-heap objects can thereby be collected incrementally despite the extra-heap references to them.

Abstract: An extended exponent floating point unit performs an extended exponent floating point operation on a plurality of operands to produce a product of the plurality of operands. The extended exponent floating point unit groups the plurality of operands into at least one group, determines a plurality of scale factors for the plurality of operands, respectively, and provides a running sum of the plurality of scale factors. The extended exponent floating point unit further scales the plurality of operands to obtain a plurality of scaled operands, multiplies the plurality of scaled operands to obtain a group product, and scales the group product to obtain a scaled group product. The scaled group product is adjusted based on the running sum. The plurality of operands are grouped such that when all the plurality of scaled operands in the at least one group are multiplied an overflow or underflow will not occur.

Abstract: A method of designing an integrated circuit, by generating a first netlist for a first router design tool, abstracting the first netlist to mask selected old routes, and generating a second netlist for a second router design tool using new routing information which excludes the masked old routes. In an exemplary use, the first routing tool is an older tool, while the second routing tool is a newer tool that can provide a more compact database and more efficient routing. The first routing tool may use a format (e.g., ASCII) which is different from the format used by the second router design tool (e.g., binary). In such a case, the channel abstraction may involve extracting all channel routes from the first format, and converting the extracted channel routes into the second format. New routes can be established using the second router design tool based on the second netlist, while preserving other old routes.

Abstract: Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.

Abstract: Improved techniques for representation of Java string objects are disclosed. The techniques are especially useful for representing Java objects in Java computing environments and can thereby improve the performance of a virtual machine, especially those operating with relatively limited resources (e.g., embedded systems with relatively smaller memory and computing power). The techniques can be implemented to create Java string objects as arrays of one-byte characters when it is appropriate. To create Java string objects, an enhanced constructor can be provided in a Java library that is available to application programs (or programmers). In addition, enhanced Java methods can also be provided in the Java library. An array representation flag can optionally be allocated in the Java string object representation. The array representation flag can indicate whether the Java string object is allocated as an array of one-byte or an array of two-byte characters.

Abstract: Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.

Abstract: Improved techniques for representing Java objects as strings are disclosed. An inventive Java Bytecode instruction suitable for execution by a Java virtual machine is disclosed. The inventive Java Bytecode instruction can be executed by a Java virtual machine to represent Java objects as strings. Moreover, Java objects can be represented as strings without invoking the Java “to_string” method which is conventionally used. This means that the costly overhead associated with repeatedly invoking Java method “to_string” is avoided. In other words, operations that are conventionally performed each time the Java “to_string” method is invoked need not be performed. As a result, the performance of virtual machines, especially those operating with limited resources (e.g., embedded systems) can be improved.

Abstract: Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.

Abstract: Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.

Abstract: The present invention describes a computer network including a network membership manager. In particular, a group of nodes on a computer network are managed by a distributed membership manager. Nodes of the computer network contain membership managers that manage the interaction between the nodes. Management of the computer network includes propagating configuration data to the nodes, providing an election process for determining the master node within a group of nodes, and monitoring the health of each node so that a change in the configuration and/or management structure can be accommodated by the nodes of the network.

Abstract: A multiprocessor, multi-program, stop-the-world garbage collection program is described. The system initially over partitions the root sources, and then iteratively employs static and dynamic work balancing. Garbage collection threads compete dynamically for the initial partitions. Work stealing double-ended queues, where contention is reduced, are described to provide dynamic load balancing among the threads. Contention is resolved by using atomic instructions. The heap is broken into a young and an old generation where parallel semi-space copying is used to collect the young generation and parallel mark-compacting the old generation. The old generation heap is divided into a number of contiguous cards that are partitioned into subsets. The cards are arranged into the subsets so that non-contiguous cards are contained in each subset. Speed and efficiency of collection is enhanced by use of card tables and linking objects, and overflow conditions are efficiently handled by linking using class pointers.

Abstract: A computer graphics system that utilizes a super-sampled sample buffer and a programmable sample-to-pixel calculation unit for refreshing the display, wherein the graphics system may adjust filtering to reduce artifacts or implement display effects. In one embodiment, the graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders a plurality of samples and stores them into a sample buffer. The sample-to-pixel calculation unit reads the samples from the super-sampled sample buffer and filters or convolves the samples into respective output pixels which are then provided to refresh the display. The sample-to-pixel calculation unit may selectively adjust the filtering of stored samples to reduce artifacts, e.g., is operable to selectively adjust the filtering of stored samples in neighboring frames to reduce artifacts between the neighboring frames.

Abstract: Systems and methods for building a platform specific compiler in a multi-platform environment are provided. A set of user defined platform dependent compiler architecture descriptors that describe corresponding architectural features of a particular hardware platform dependent compiler are provided. The descriptors are converted into the platform dependent compiler source code which is compiled into platform dependent compiler object code. The platform specific compiler is formed from the platform dependent compiler object code and platform independent compiler object code already provide. During compiler run time an interface mediates the flow of information between the platform dependent compiler object code and the platform independent compiler object code.

Abstract: A clamping circuit which is connected to each long line, preferably adjacent the receiver. The clamping circuit biases the long line at the trigger threshold of the receiver. Thus, instead of amplifying the signal as a repeater will do, the present invention clamps the line to the threshold, thus allowing a faster response since the line doesn't have to be charged or discharged from a lower or higher level to the threshold. This thus speeds up the transition at the receiver without requiring a repeater or a keeper.