Abstract: The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block.

Abstract: The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block.

Abstract: An invention is provided for restoring execution of an application program after interruption in a distributed processing framework. The invention includes a post mortem object that stores point of execution information for an application program. The point of execution information is periodically updated to reflect a current point of execution within the application program at a time of the update. In addition, an agent process is included that executes on a processing resource, such as a test system. The agent process is capable of utilizing the post mortem object to reinitialize the application program to begin execution from a position described by the point of execution information.

Abstract: A method for determining the desired decoupling components for stabilizing the electrical impedance in the power distribution system of an electrical interconnecting apparatus, including a method for measuring the ESR for an electrical device, a method for determining a number of desired decoupling components for a power distribution system, and a method for placing the desired decoupling components in the power distribution system. The method creates a model of the power distribution system based upon an M×N grid for both the power plane and the ground plane. The model receives input from a user and from a database of various characteristics for a plurality of decoupling components. The method determines a target impedance over a desired frequency range. The method selects decoupling components. The method determines a number for each of the decoupling components chosen. The method places current sources in the model at spatial locations corresponding to physical locations of active components.

Abstract: A memory architecture in accordance with an embodiment of the present invention improves the speed of method invocation. Specifically, method frames of method calls are stored in two different memory circuits. The first memory circuit stores the execution environment of each method call, and the second memory circuit stores parameters, variables or operands of the method calls. In one embodiment the execution environment includes a return program counter, a return frame, a return constant pool, a current method vector, and a current monitor address. In some embodiments, the memory circuits are stacks; therefore, the stack management unit to cache can be used to cache either or both memory circuits. The stack management unit can include a stack cache to accelerate data transfers between a stack-based computing system and the stacks. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control.

Abstract: An event correlation system for network management has computer code for at least one model of a process to be run on a node of a network, where said process is intended to be run on a different node of the network than the model. The correlation system also has code for an alarm monitor comparing the apparent behavior of the model to actual events generated by the process and generating alarm messages when the actual events of the process do not match expected events from the model. It also has code for an event correlation utility; and means for communicating alarms from the alarm monitor to the event correlation utility.

Abstract: A parallel FFT generating system is disclosed for generating a Fast Fourier Transform (FFT) of an input vector. The parallel FFT generating system includes a plurality of processes configured to receive the input vector and process the input vector in parallel in relation to a set of twiddle factors to generate an output vector, the output vector comprising a Fourier transform representation of the input vector.

Abstract: A method of designing an integrated circuit calculates the current density in each metal lead. The method can calculates a mean time to failure for at least one metal lead. Calculation of the mean time to failure can include the current density and the temperature. The method can assume the metal leads are arranged in series only. The method can calculate the reliability of the integrated circuit based on temperature effects. The method can arrange the set of metal leads by reliability. The method can divide the set of metal leads into at least two subsets, a subset requiring redesign and a subset meeting the reliability criteria. An embodiment includes an integrated circuit designed by the method taught. An embodiment includes a computer program product according to the method taught. An embodiment includes an integrated circuit including an integrated circuit designed according to the computer program product.

Abstract: In a compression system, three-dimensional geometry is first represented as a generalized triangle mesh, a data structure that allows each instance of a vertex in a linear stream to specify an average of two triangles. Individual positions, colors, and normals are quantized, preferably quantizing normals using a novel translation to non-rectilinear representation. A variable length compression is applied to individual positions, colors, and normals. The quantized values are then delta-compression encoded between neighbors, followed by a modified Huffman compression for positions and colors. A table-based approach is used for normals. Decompression reverses this process. The decompressed stream of triangle data may then be passed to a traditional rendering pipeline, where it is processed in full floating point accuracy.

Abstract: A system generates an audio signature for a data item based on a source identifier associated with the data item. The system receives a source identifier along with a data item and maps the source identifier to the audio signature using a mapping function that allows a user to distinguish the audio signature from other audio signatures generated for other sources. The mapping functions always map the same source identifier to the same audio signature. The system outputs the audio signature to a user. This enables the user to associate the audio signature with the source. The data item can include, an electronic mail message, a pager signal, a telephone call, a data item in an instant messaging system, an indicator of an entry of a new participant into a conference call or a chat room, or an electronic cookie that identifies a client computer system to a web site.

Abstract: An apparatus for multiplying a first number and a second number together is described, each of the numbers having a width of 8, 16, 32, 64 or 128-bits or more. The 32-bit embodiment of the apparatus includes a booth recorder having two inputs and 16 outputs, the recorder determining 16 individual booth groups associated with the second number and providing one partial product per booth group on individual ones of the 16 outputs.

Abstract: Rendered wire frame models of objects offered for sale can be downloaded and displayed as virtual objects in the context of an environment in which a real object would be actually used. The rendered models are located and oriented so that they appear exactly as a real object would appear when placed in the environment. A video camera captures the environment and a two dimensional perspective view of the rendered wire frame model is combined with an image of the environment to show how the object will look when actually installed.

Abstract: A multiple compressor refrigeration heat sink module is suitable for use in standard electronic component environments. The multiple compressor refrigeration heat sink module is self-contained and is specifically designed to have physical dimensions similar to those of a standard air-based cooling system. As a result, the multiple compressor refrigeration heat sink module can be utilized in existing electronic systems without the need for significant system housing modification or the “plumbing” associated with prior art liquid-based cooling systems. The multiple compressor refrigeration heat sink module is also well suited for applications that require a highly reliable, energy and space efficient, cooling systems for electronic components such as multi-chip modules and mainframe computer applications.

Abstract: A modular computer system mechanical interconnection includes a primary chassis having a first opening and a secondary chassis attached to the primary chassis and having a second opening, wherein the first opening and the second opening are generally aligned. The apparatus further includes a backplate covering the aligned first opening and second opening.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.

Abstract: A graphics system and method for panning from one portion of a stored image to another portion of the image includes a frame buffer, one or more display devices, one or more raster parameter registers, and one or more raster parameter updaters. The image is stored in the frame buffer and each display device is configured to display less than the entire image. A panning operation is initiated by requesting an update of one or more of the raster parameter registers during a next blanking period.

Abstract: The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and methods of coupling semiconductor devices. In a particular embodiment, the semiconductor device is a multi-chip semiconductor that comprises a first semiconductor device and a second semiconductor device. The first semiconductor device has a first surface. The first surface contains a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members. The second semiconductor device has a second surface, the second surface containing a third ridge alignment member, the second semiconductor device positioned such that at least a portion of the third ridge alignment member is located within the receiving area of the first semiconductor device.

Abstract: A dynamic sense amplifier is provided that reduces the amount of time required to perform a memory cell restoration in a DRAM following a read operation. The dynamic sense amplifier can be isolated from the bit lines that it is sensing to avoid the capacitance affects of the bit line during a restoration operation. By avoiding the capacitance effects of the selected bit line during a restoration operation the dynamic sense amplifier is able to restore the just read memory cell to its original state in a more efficient manner.

Abstract: A system and method for calculating a deadlock-free set of paths in a network which generates an ordered set of deadlock-free sub-topologies, referred to as “layers.”The ordered set of layers is used to determine a deadlock-free set of paths through the network. The resulting paths allow data to be efficiently routed through the network without causing traffic to be disproportionately routed through any subset of links. Each of the deadlock-free layers may be any type of deadlock-free sub-topology. The generated ordering may be any arbitrary ordering of the layers. A shortest-path route calculation is performed with the following constraint: starting at any given layer, for each node, proceed to calculate a shortest path to every other node in the graph where at any node being utilized to assess a given minimum path, the path may move to any higher-ordered layer, but may never return to a lower ordered layer. In this way, within each layer, a path moves through a tree and thus avoids deadlock.