Abstract: Methods, systems, and articles of manufacture consistent with features of the present invention configure log files with header information that allow a logging service to directly access various locations of the log file. Also, log records contained in the log file may be configured with fields that allow the logging service to directly access a log record, as well as confirm its identity. Additionally, the logging service may be configured to process various requests for log records from a client using the log record fields. The logging service may use offset fields in each log record to perform efficient traversal operations while processing the requests. Furthermore, various fields in each log record may be used by logging service to perform consistency checks to verify the configuration of each log record.

Abstract: An invention is provided for customizing Java API implementations. A plurality of class files is obtained, wherein the class files are capable of being used together to provide a plurality of functional behaviors to an application. A feature marker is then associated with each of the class files based on a functionality provided by the class file. Each feature marker indicates a particular functionality provided by the plurality of class files. Particular class files are then selected from the plurality of class files based on the feature markers associated with the particular class files. In one aspect, the plurality of class files can comprise a first JAR file, and the selected class files can be used to generate a second JAR file. The second JAR file can also exclude class files that are not selected. Further, non-Java based native files, if any, utilized by the plurality of class files can also be customized to a subset of the original native files in a similar manner.

Abstract: A system and method for processing batch requests in a CIM system environment is disclosed. Methods, systems and articles of manufacture consistent with the present invention configure a client with a modified API that creates new CIMOperation objects for each operation included in a batch request. The CIMOperation objects are placed in a batch list of operations that are sent to a CIM object manager for processing. Furthermore, the modified client API returns an operation ID to the client for each operation included in the batch list. The CIM object manager, based on the type of protocol used by the client, processes each CIMOperation object included in the batch list to obtain a corresponding result. Each result is placed in a corresponding CIMOperation object included in the batch list received from the client. The batch list of CIMOperation objects embedded with the results is sent back to the client which may use the operation IDs to retrieve the result data located within each CIMOperation object.

Abstract: Methods, systems and articles of manufacture consistent with the present invention configure a computing system with a logging service that interacts with implementation objects associated with particular types of storage devices through a storage interface. The implementation objects may include processes used to access the storage devices during logging operations. The logging service may also be configured to adjust which storage device is to be used for logging operations without restarting the computing system. This adjustment may be made through a property file that includes properties specific to individual types of storage devices. The property file may be modified to include new properties by a system administrator or by the logging service during runtime operations of the computing system. The new properties may designate new storage devices to be used by the logging service to perform subsequent logging operations.

Abstract: A system and method for selectively granting access to a target object. In one embodiment, the system includes an object data store, an access control instruction data store, an action data store, a context, and an access determination engine. The object data store includes a plurality of hierarchically structured target objects and a plurality of hierarchically structured actor objects. The access control instruction data store includes a plurality of hierarchically structured access control instructions. The action data store comprising a plurality action objects. The context includes an actor attribute, an action attribute, and a target attribute. The access determination engine configured to selectively grant access to the target object based on a first set of access control instructions having attributes that match the context and a second set of access control instructions having attributes that are hierarchically broader than the attributes of the context.

Abstract: An electronic apparatus for receiving source synchronous signals is provided. The receiver continuously monitors the phase relationship between each data signal and the source synchronous clock signal. In this manner, the electronic apparatus can compensate for phase discrepancies that occur over time without having to interrupt any data operations.

Abstract: An invention is provided for customizing attributes of a distributed processing system. An embodiment includes a lookup service capable of advertising attributes of a processing resource, and a processing resource executing an agent process, which is in communication with the lookup service. The processing resource is capable of loading a set of core attributes defining characteristics of the processing resource. Further included are a plurality of dynamic attribute classes and a dynamic attribute list file that provides information concerning the dynamic attribute classes. In use, the agent process reads the dynamic attribute list to obtain the information concerning the dynamic attribute classes, and then loads the plurality of dynamic attribute classes utilizing the information in the dynamic attribute list concerning the dynamic attribute classes.

Abstract: A circuit includes a drive transistor coupled between an output and a first potential, a constant current circuit coupled between the gate of the drive transistor and a second potential, and a compensation circuit coupled between the gate of the drive transistor and the first potential. The constant current circuit draws a current from the gate of the drive transistor to the second potential that is substantially independent of process and temperature variations, and therefore turns on the drive transistor at a constant rate, regardless of process and temperature variations. The compensation circuit draws a small current from the gate of the drive transistor to the first potential that is dependent upon process and temperature variations of the drive transistor, and therefore reduces the discharge rate of the gate of the drive transistor according to process and temperature variations of the drive transistor.

Abstract: A graphics system comprises a texture memory, a rendering engine, a sample buffer and a filtering engine. The rendering engine renders received primitives based on a render pixel array whose vertical and horizontal resolutions are dynamically programmable. The rendering engine determines render pixels that geometrically intersect a primitive. For each intersecting render pixel, a texture access may be required (if texture processing is turned on) to determine texture values. The texture values may be used to compute sample values at sample positions interior to the sample render pixel and the primitive. A controlling agent may decrease the vertical and horizontal resolutions of the render pixel array to control frame render time. The filtering engine may programmably generate virtual pixel centers covering the render pixel array. Any change in the render pixel resolutions may require an accommodating change in the virtual pixel array parameters.

Abstract: One embodiment of the present invention provides a system that facilitates communications between a cluster of nodes within a clustered computing system in a manner that tolerates failures of communication pathways between the nodes. The system operates by configuring a distinct logical pathway between each possible source node and each possible destination node in the cluster, so that each distinct logical pathway is routed across one of at least two disjoint physical pathways between each possible source node and each possible destination node. In doing so, the system configures a first logical pathway between a first node and a second node across a first physical pathway of at least two disjoint physical pathways between the first node and the second node. Upon detecting a failure of the first physical pathway, the system reroutes the first logical pathway across a second physical pathway from the at least two disjoint physical pathways between the first node and the second node.

Abstract: According to aspects of the present invention, an original archive file having one or more entries is created, where each entry in the original archive file is itself a file, and where each entry in the archive file may comprise any file type, including an archive file. The original archive file is transmitted to a client computer. Subsequently, a target archive file is created, wherein one or more of the entries in the target archive file are typically expected to be identical to one or more entries in the original archive file. Given the original archive file and the target archive file, a difference archive file is created. The difference archive file comprises an index file describing the changes between the original archive file and the target archive file, and also comprises a set of entries corresponding to the entries in the target archive file that are not contained in the original archive file.

Abstract: An apparatus, system, and method for speeding up data transfers while reducing bus contention during repeated consecutive read-write operations. By reducing the length of time during which selected data pulses are driven on the memory bus, a higher percentage of usage of the memory bus may be attained without increasing the likelihood of bus contention and resulting degradation or damage to the memory system. The selected data pulse is preferably the write data pulse driven on the memory bus by the memory controller. A zero bus turnaround protocol may be implemented. The memory controller may include interface circuitry and write control circuitry that outputs an associated control signal to a three-state buffer. The three-state buffer, after being enabled by the associated control signal, drives write data on a data line of a memory bus. The turn-on delay associated with the three-state buffer exceeds the turn-off delay also associated with the three-state buffer.

Abstract: A memory controller for a memory subsystem of a computer system connects to a processor bus. The memory controller is for use with memory devices such as RDRAM or DDR SDRAM that allow for multiple open pages. Memory references are remapped by an address mapper and processed by a page tracking buffer to keep track of open pages in the memory devices. The controller also has a state machine, and an interface to memory devices. The page tracking buffer has a row address content addressable memory for determining when a reference is in an open page, and a bank content addressable memory for determining when a reference is to the same bank as an open page. The controller closes open pages of a bank prior to opening new pages in that bank. The page tracking buffer has fewer lines than the product of the maximum number of memory devices times the maximum number of simultaneously open pages of each device, but provides for tracking any page of any of the memory devices.

Abstract: An apparatus and system comprising electrical interconnection devices (EIDs), such as printed wiring boards, semiconductor packages, and printed circuit boards, having novel via and signal trace positioning. The vias may be positioned off-center from the pattern of the surface pads. Via groups, or staircase vias, connect surface pads with vias extending into the electrical interconnection device. The via groups convert the pad geometry on the surface to a more open via pattern on one or more internal layers. The EID comprises a plurality of pads formed on a surface for providing electrical connections to another EID. A plurality of vias each extend from a corresponding pad to another layer of the printed wiring board. Each via is offset from a central location of its corresponding pad.

Abstract: A multiprocessing computer system includes a plurality of processing nodes, each having one or more processors, a memory, and a system interface. The plurality of processing nodes may be interconnected through a global interconnect network which supports cluster communications. The system interface of an initiating node may launch a request to a remote node's memory or I/O. The computer system implements an error communication reporting mechanism wherein errors associated with remote transactions may be reported back to a particular processor which initiated the transaction. Each processor includes an error status register that is large enough to hold a transaction error code. The protocol associated with a local bus of each node (i.e., a bus interconnecting the processors of a node to the node's system interface) includes acknowledgement messages for transactions when they have completed.

Abstract: A system for programmatically adjusting electrical characteristics of a bus interface so as to modify bus operating and signaling parameters employs a control module or mechanism, responsive to a digital signal, for setting the characteristic's value. The electrical characteristic can be a voltage determinative, for example, of any of the following bus operating and signaling parameters: driver output rise time, driver output fall time, driver voltage limits, driver propagation time, receiver threshold voltage levels, or termination resistance. The digital signal can be generated, for example, by a computer-executable program, a controller, or other such device, that applies the digital signal to the control mechanism, for example, via a JTAG interface/controller.

Abstract: An automated method of analyzing crosstalk in a digital logic integrated circuit, the method operating on a digital computer, is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. For at least one potential victim wire of the plurality of wires, determining a subset of the wires of the chip are found to be potential aggressor wires that may couple to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire.

Abstract: Communication between application programs is facilitated by a virtual device driver to which the application programs make function calls. The device driver registers each application in response to a request for application-to-application communication. During registration, the device driver determines the addressing mode of the application being registered. An address mapping operation is performed and the results of the mapping operation along with other information about the application are stored in a data store administered by the kernel of the device driver. The device driver allows two applications of dissimilar addressing mode to communicate with one another without a priori knowledge of the communicating partner's addressing mode. The virtual device driver handles communication transparently for the communicating applications, allowing the applications to send and receive data.

Abstract: A system and method for reducing the number of memory accesses by a hardware device to a descriptor memory is disclosed. Methods, systems and articles of manufacture consistent with the present invention enable software to embed a subsequent descriptor it is posting in the descriptor memory into a current descriptor listed in the descriptor memory. Additionally, hardware is configured to transmit a data packet associated with the current descriptor to a recipient device. When hardware receives an acknowledgment message from the recipient device associated with the transmitted data packet, it fetches the current descriptor to update a completion code within the current descriptor using a Read-Modify-Write (RMW) transfer sequence. As part of the RMW memory operation, hardware may use the embedded copy of the subsequent descriptor within the current descriptor to transmit the next data packet associated with the subsequent descriptor.

Abstract: A signature capture and analysis system suitable for use in a high performance computer graphics system is described. The system employs a distributed network of signature analysis registers (SARs) which may be configured to capture and accumulate information from one or more channels of data over pre-defined periods of time. The SARs may be so distributed to allow for the isolation of faults to a sub-system level. The signature values developed in these SARs are, in some cases pre-seeded, and may include contributions from both data and control signals. Checking of the signature values against known good or expected outcomes is provided for. In some cases the SARs may be implemented as linear hybrid cellular automatons.