Abstract: A method for analyzing a scan dump assigns a first latch to a first value, compares the first latch output to the first value for spatial alignment. The method then assigns a second latch to either a second or third value. The second value corresponds to before an event. The third value corresponds to after an event and may be incremented with ongoing clock cycles.

Abstract: An automated method of analyzing crosstalk in a digital logic integrated circuit on a digital computer is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. The netlist has gate and black box invocations as well as transistor invocations. Library models are used to find driving resistances and capacitances associated with the gate and black-box invocations. For at least one potential victim wire of the plurality of wires, a subset of the wires of the chip are found to be potential aggressor wires to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire.

Abstract: A method for secure data communication with a mobile machine in which a data packet is received from the mobile machine having a particular network address. A pool of secure addresses is established and a data structure is created to hold address translation associations. Each association is between a particular network address and a particular one of the secure addresses. If the received data packet is a secure data packet an association between the received data packet's network address and a secure address in the data structure is identified and the data packet's network address is translated to the associated secure address before forwarding the data packet on to higher network protocol layers. When the received data packet is not secure it is passed it on without address translation to the higher network protocol layers. For outgoing packets addressed to a secure address, the secure address is translated to a real network address (e.g.

Abstract: An apparatus or method for testing the setup time and hold time specifications of a chip. An apparatus according to the invention would include a first chip, a second chip, and multiple links coupling the first chip to the second chip. One of the links carries a clock signal between the chips. Other links carrying data have propagation delays different from the propagation delay of the link carrying the clock signal. The relation of the delays for the data links to the delay for the clock link determines a particular setup and/or hold time tested.

Abstract: Systems and methods consistent with the present invention use a Namespace paradigm to define an external component reference to a style sheet. When the style sheet processor processes the tags in the style sheet, it recognizes the external component declaration. The style sheet will contain a name of the external component instance and a definition of the method to execute associated with the external component instance, and may contain arguments for the method associated with the external component instance which is executing. The XSLT processor then relinquishes control to the external component to execute the method defined in the style sheet. The results of the method's execution may be placed in the transform document generated by processing the style sheet. However, this is not required and other results may be generated, including those not related to the transform document.

Abstract: An integrated sub-network for a vehicle. The sub-network includes one or more devices which are addressable using IP addresses or object terminology. The sub-network may appear as a single IP address to an external network. The devices may include various servers and clients, such as microphones, cameras, GPS receivers, interfaces to on-board diagnostic systems, communication devices, displays, CD players, radios, speakers, security devices and LANs (local are networks,) to name only a few. Devices may easily be connected or disconnected to upgrade or reconfigure the vehicle's systems, and software and services can easily be provided to the various devices through the network. The network can enable the interaction of various network devices to increase the capabilities or utility of devices which may otherwise be limited. The system therefore provides an easy and inexpensive means to improve or otherwise modify the functionality of the vehicle.

Abstract: A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.

Abstract: A method and apparatus for operating a local server computer of a client-server network includes a technique to receive a request from a client computer of the client-server network. A determination is made whether the request requires dynamically generated information from a servlet object of the client-server network. If so, a specified servlet object corresponding to the request may be uploaded from a remote server computer of the client-server network. The specified servlet object is then executed to obtain dynamically generated information corresponding to the request.

Abstract: A system for providing a floating point remainder comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and the second floating point operand, respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the remainder of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand.

Abstract: In an electronic system with multiple power supplies, a method and apparatus dynamically determines the number of power supplies required to power up the system without overloading any supply. The individual power supplies do not turn on until the determined number of power supplies have received AC power and become operational before attempting a complete system power on. The amount of required power is determined before power up based on the actual power load present. The actual load is determined by sensing load indicators in each load device and computing the total power load. The amount of power from supplies which have received AC power is determined by detecting when AC power has been applied to each power supply and computing the total amount of power available. System power up is delayed when the number of power supplies which have received AC power is insufficient to power the system without an overload situation occurring.

Abstract: A system for generating a Walsh transform output vector from an “N”-component input vector includes a vector store, a plurality of Walsh transform kernels and a control module. The vector store is configured to store the input vector The Walsh transform kernels are configured to generate a Walsh transform of a predetermined radix, with at least two of the Walsh transform kernels generating respective Walsh transforms of different radices A and B, B<A.

Abstract: A system and method for testing signal interconnections using built-in self test (BIST). BIST functionality is designed into the various chips of a computer system. These chips include a transmit unit, a receive unit, a control logic unit, and a central logic unit. A control logic unit associated with a signal block (i.e. a group of signals) configures the signal block for either testing or normal operation. The central logic unit performs test pattern generation for all signal blocks on a given chip. Chips may act as either a master or slave chip during testing. When acting as a master chip, the transmit unit of the chip drives test patterns onto one or more signal lines. The receive unit of the slave chip returns a corresponding test pattern to the master chip after receiving the transmitted test pattern. A receive unit on the master chip receives the corresponding test patterns and performs verification. All tests occur at the operational clock speed of the computer system.

Abstract: A multicast repair tree is established, the repair tree having one sender station and a plurality of repair head stations. A repair head station has an affiliated group of member stations. A repair head station retransmits a lost message to its affiliated group of member stations upon receipt from a member station of a NACK message indicating that the selected message was not received. Acknowledgment windows (ACK windows) are established in a member station for transmission of ACK or NACK message by the member station. A number of messages transmitted by the sender station during a transmission window is established. Also a same size of ACK window is established in the receiving stations, with a slot in the ACK window corresponding to each message transmitted by the repair head station. Each receiving station is assigned a slot in the ACK window during which time that receiving station transmits its ACK or NACK messages.

Abstract: A electro-desorption compression system according to the present invention comprises an enclosure which includes first and second spaced-apart electrical conductors, a sorbent which is positioned in the enclosure between the first and second conductors, a sorbate which is capable of combining with the sorbent in an adsorption reaction to form a sorbate/sorbent compound, a power supply which is connected to the first and second conductors and which generates an electrical current that is conducted through the sorbate/sorbent compound to desorb the sorbate from the sorbent in a desorption reaction, and a pressure chamber which is connected to the enclosure and which receives the sorbate from the enclosure during the desorption reaction and releases the sorbate into the enclosure during the adsorption reaction.

Abstract: A process tracking reference voltage generator has been developed for an input/output system. The voltage generator includes a driver component that transmits an output signal to a receiver component. The receiver component generates a reference voltage in relation to the output signal as it varies with changing system operating conditions.

Abstract: A Compact Personal Computer Interface (CPCI) microprocessor board installation device is disclosed herein. A preferred aspect comprises an inner surface defined by a top plane, a bottom plane, a back plane, and at least one side plane, where the inner surface has means disposed therein for accepting, aligning, and releasably engaging a CPCI board, with a device according to the present invention, an installer may insert a CPCI board into the present invention, and install the board into a back plane while being assured that the board is protected from both physical and ESD damage. After successfully installing the CPCI board, the installer may then release the present invention from the board, and reuse the present invention on another installation.

Abstract: A memory allocation scheme for object allocation in concurrent object-oriented server-side environments that combines the time efficiency of thread-local allocation schemes with the space efficiency of shared-heap allocation schemes has been developed. A pool of memory allocation spaces is maintained so that when a thread transitions to a runnable state, it is allocated a private memory space. However, when the thread transitions out of the runnable state and no longer needs its allocated memory, the space is re-allocated back to the pool for use by another runnable state thread.

Abstract: The present invention is a method and apparatus for unidirectional coolant flow control unit for pressurized cooling systems. The invention comprises a valve on a coolant flow control unit. The valve remains in the open position during normal function of the coolant flow control unit. If the coolant flow control unit fails, the valve closes. Thus, the cooling system performs better than prior art cooling systems in the event of a failure of one or more coolant flow control units. In one embodiment, multiple improved coolant flow control units can be implemented wherein a flow of coolant enters one side of the system and exits the other side. In the even of a failure, the closure of the valve is caused by the shifting pressure within the system, which forestalls the cooling problems associated with prior art redundant coolant control flow systems.

Abstract: Techniques for initialization of Java classes are disclosed. As such, the techniques can be implemented in a Java virtual machine to initialize Java classes represented in Java class files. A Java class loader suitable for loading class files into the Java virtual machine is disclosed. As will be appreciated, the Java class loader facilitates loading and execution of the Java initialization methods that need to be executed in order to initialize Java classes. Moreover, the Java class loader operates to remove the Java initialization methods after they have been executed and no longer serve a useful purpose. This means that the virtual machine can utilize its memory space more efficiently. As a result, the performance of virtual machines, especially those operating with limited resources is improved.