Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits.

Abstract: A branch prediction scheme predicts whether a computer instruction will cause a branch to a non-sequential instruction. A prediction counter is selected by performing an exclusive or (XOR) operation between bits from an instruction address and a hybrid history. The hybrid history, in turn, is derived by concatenating bits from a global history register with bits from a local branch history table. The bits from the local branch history table are accessed by using bits from the instruction address.

Abstract: A network address is captured from a source document or signal and is stored in a data structure such as a list for subsequent use. When a network resource at the network address is subsequently visited, the network address is automatically deleted from the list. The list storage and deletion functions are integrated into a World Wide Web browser. If a connection cannot be established using the network address, the connection is retried, and the network address is marked for delection after a pre-determined number of retries. Thereafter, if another connection attempt fails, a user may delete the network address or retain it for another retry after a user-defined time. Identified network addresses are accessed over the network to validate their correctness and a snapshot of the page displayed is stored and related to the network address.

Abstract: One embodiment of the present invention provides resistor within an integrated circuit with a substantially linear resistance. This resistor includes a diode-connected transistor coupled in parallel with a current-source-connected transistor, so that a nonlinear resistance of the diode-connected transistor combines with a nonlinear resistance of the current-source-connected transistor to produce a substantially linear combined resistance. It also includes selection circuit that is configured to selectively deactivate the resistor by deactivating the diode-connected transistor and the current-source-connected transistor. This selection circuit provides a range of possible resistance values, and thus enables the resistance to be quickly switched on and off to allow for use in a high-speed driver circuit.

Abstract: A method and system for providing limited access privileges with an untrusted terminal allows a user to perform privileged operations between the untrusted terminal and a remote terminal in a controlled manner. The user can establish a secure communications channel between the untrusted terminal and a credentials server to receive credentials therefrom. Once the user receives the credentials, the secure communications channel is closed. The user can then use the credentials to perform privileged operations on a remote terminal through the untrusted terminal. The remote terminal knows to grant the user limited privileges based on information included in the credentials. The effects of malicious actions by the untrusted terminal are limited and controlled.

Abstract: In order to maintain locking invariants in a multi-threaded system, a special inverse lock class is defined whose constructor stores a reference to, and then releases, a previously-acquired lock whose reference is passed into it. The destructor of the class re-acquires the referenced lock. During operation, the class is instantiated, passing in the desired lock before an upcall is made. Instantiation executes the constructor and causes the lock to be released. When the upcall terminates, either normally or by an exception, the inverse lock object destructor is executed causing the lock to be re-acquired. Since the inverse lock object destructor will always be called when the object is destroyed, the locking invariant will always be satisfied.

Abstract: Methods and apparatus for locking and unlocking objects using synchronized threads are disclosed. According to one aspect of the present invention, a computer-implemented method for using a first thread to obtain a header value of an object includes replacing contents of a header of the object with a sentinel which identifies an execution stack associated with the first thread. Once the object contents are replaced with the sentinel, a determination is made regarding whether the object contents include a header value of the object, and when it is determined that the object contents do not include the header value of the object, a determination is made as to when the object is in the process of being studied by a second thread. In one embodiment, when it is determined that the object is not in the process of being studied by the second thread, the method involves adding the first thread to a list associated with the stack.

Abstract: Methods and apparatus for the efficient allocation of shared memory in a multi-threaded computer system are disclosed. In accordance with one embodiment of the present invention, a computer-implemented method for allocating memory shared by multiple threads in a multi-threaded computing system includes partitioning the shared memory into a plurality of blocks, and grouping the multiple threads into at least a first group and a second group. A selected block is allocated to a selected thread which may attempt to allocate an object in the selected block. The allocation of the selected block to the selected thread is based at least partially upon whether the selected thread is a part of the first group or the second group. In one embodiment, grouping the multiple threads into the first group and the second group includes identifying a particular thread and determining whether the particular thread is a fast allocating thread.

Abstract: A substrate for packaging a storage or server system may include one or more sections of the substrate configured to hold a two-dimensional array of disk drives. Another section of this substrate may be configured to hold circuitry for accessing the array of disk drives. This circuitry may include one or more processors. The substrate also includes a first plurality of ribs positioned in the first access of the substrate. The first plurality of ribs separate the sections from one another. The section configured to hold the control circuitry may also be configured to hold one or more power supplies for supplying power to the array of disk drives and control circuitry. This section, as well as other sections, may be divided in two by one or more additional ribs in a transverse direction. The substrate may be configured to be mounted in a cage or rack and may include an edge connector at one edge of the substrate to provide electrical connectivity to a back plane in the cage or rack.

Abstract: A multiprocessor computer system comprises a plurality of network interfaces each adapted to be coupled to respective external networks for receiving and sending data packets to and from remote devices coupled to the external networks via a particular communication protocol. The multiprocessor computer system further comprises a plurality of symmetrical processors including a control processor and at least one switching processor. The switching processor further includes at least one network application executing thereon. The control processor further includes an operating system portion having a kernel memory and at least one network driver communicating with the plurality of network interfaces. A buffer descriptor list is accessible by the network application and the network driver.

Abstract: An automated shielding tool, algorithm, and design methodology for shielding integrated circuits is disclosed herein. This is accomplished by inserting VDD and VSS wire proximate to signal wires on the same metal layer. The noise issues for dynamic circuits is described along with the benefits and costs of wire shielding. The methodology of the shield tool is a systematic approach for dealing with noise due to capacitive and inductive coupling.

Abstract: A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating point operand. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the square root of the first floating point operand and a resulting status embedded within the resulting floating point operand.

Abstract: The present invention provides logic to write data to a multi-ported memory array. The memory array is comprised of a plurality of memory banks and a common write word line shared by the memory banks. The memory array includes a plurality of write buffers, wherein each write buffer is associated with one of the memory banks. The memory array further comprises a selector module for selecting a write buffer to write data into its associated memory bank. The memory array further includes a writing module within the write buffer for writing data into the selected memory bank by way of a signal to the memory bank.

Abstract: A method and computer graphics system capable of super-sampling and performing real-time convolution are disclosed. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The sample buffer, which is coupled to the graphics processor, may be configured to store the samples. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the sample buffer to filter into an output pixel. The sample-to-pixel calculation unit performs the filter process in real-time, and may use a number of different filter types in a single frame. The sample buffer may be super-sampled, and the samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid.

Abstract: A method and apparatus for performing remote data replication. The method and apparatus can detect an interruption in the remote data replication process and begin local logging of all local data writes that occur while the remote data replication process is unavailable. The method and apparatus can perform remote data replication across multiple remote storage devices or the method and apparatus can replicate a data structure from a first storage device to multiple locations on one or more remote storage devices. In addition, the method and apparatus can halt the remote data replication and copy data from the local storage device to the remote storage device to ensure data uniformity on all storage devices.

Abstract: A method and apparatus for performing remote data replication. The method and apparatus can detect an interruption in the remote data replication process and begin local logging of all local data writes that occur while the remote data replication process is unavailable. The method and apparatus can perform remote data replication across multiple remote storage devices or the method and apparatus can replicate a data structure from a first storage device to multiple locations on one or more remote storage devices. In addition, the method and apparatus can halt the remote data replication and copy data from the local storage device to the remote storage device to ensure data uniformity on all storage devices.

Abstract: A processing system is provided. The processing system includes a master system and a processing resource. The master system is designed to execute a service component and a system controller component. The processing resource is designed to register with the service component for a specific period of time. By registering with the look up service of the service component, the processing resource advertises the eligibility of the processing resource to execute a software processing job having a set of requirements. The system controller component is designed to search the look up service of the service component to locate the processing resource having a set of attributes that substantially matches the set of requirements of the software processing job.

Abstract: A system for providing a floating point product comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the product of the first floating point operand and the second floating point operand. Additionally, the results circuit provides a resulting status embedded within the resulting floating point operand.

Abstract: A method for secure data communication with a mobile machine in which a data packet is received from the mobile machine having a particular network address. A pool of secure addresses is established and a data structure is created to hold address translation associations. Each association is between a particular network address and a particular one of the secure addresses. If the received data packet is a secure data packet an association between the received data packet's network address and a secure address in the data structure is identified and the data packet's network address is translated to the associated secure address before forwarding the data packet on to higher network protocol layers. When the received data packet is not secure it is passed it on without address translation to the higher network protocol layers. For outgoing packets addressed to a secure address, the secure address is translated to a real network address (e.g.