Abstract: A latch control circuit for overcoming phase uncertainty between crossing clock domains, which includes an interface and control circuit for controlling and communicating data between the clock domains and, which also includes either static or dynamic initialization circuitry.

Abstract: One embodiment of the present invention provides a system that asynchronously distributes data to a plurality of destinations within a digital circuit. Upon receiving a data item to be distributed, the system monitors asynchronous control signals associated with the destinations, wherein a given asynchronous control signal indicates that a given destination is free to receive the data item. For each destination that is free to receive the data item, the system forwards the data item to the destination asynchronously without waiting for a system clock signal, and also changes an asynchronous control signal associated with the destination to indicate that the destination is not free to receive a subsequent data item.

Abstract: A method of reordering instructions. Barrier instructions are determined. The method determines when a processor stall may occur, and hoists subsequent instructions to fill in the stall time. However, instructions are not hoisted above the barrier instructions. Barrier instructions include branch instructions, store and load instructions, and instructions which, if hoisted, cause the number of available registers to be exceeded. The method produces a reordered instruction trace and statistics regarding the effectiveness of the reordering.

Abstract: A graphics system applies multiple layers of texture information to triangles. The graphics system includes a hardware accelerator, a frame buffer and a video output processor. The hardware accelerator receives vertices of a triangle, identifies fragments of a sampling space which intersect the triangle, and applies the multiple layers of texture to the intersecting fragments. The multiple layers of textures may be stored in a texture memory external to the hardware accelerator. The hardware accelerator switches to a next texture layer after applying the textures of a current layer to all the fragments of the triangle. The hardware accelerator includes (or couples to) a texture accumulation buffer which stores color values associated with the triangle fragments between the application of successive texture layers. The frame buffer stores the samples and pixels generated from the samples by filtration. The video output processor transforms the pixels into a video signal.

Abstract: An interactive applet for testing a user in a web-based learning environment. The interactive applet is embedded in a course page of a web-based curriculum. The applet provides question to a user regarding the information presented in the course, followed by a text field. The applet instructs the user to enter an answer to the question in the text field. The applet provides feedback to the user, and allows the user to revise an incorrect answer.

Abstract: Improved techniques for invocations of native methods in Java computing environments are disclosed. The techniques can be implemented in Java computing environments to facilitate efficient use of methods (functions or subroutines) written in programming languages other than Java (e.g., C, C++, etc.). As such, the techniques are highly suitable for use by virtual machines operating with relatively less memory and/or computing power (e.g., embedded systems). A lightweight native method invocation interface can be implemented to provide direct access to Java parameters on the execution stack. In addition, the lightweight native method invocation can include macro instructions that operate efficiently to convert the Java parameters into native parameters. Thus, the lightweight native method invocation can significantly reduce the overhead associated with conventional Java native method invocation techniques.

Abstract: A central processing unit (CPU) is provided and is coupled to a display for displaying graphic and other data in multiple overlapping windows. The CPU is further coupled to one or more input devices which permits a user to selectively position a cursor and input and manipulate data within each of the windows on the display. The windows include defined areas having window features such as text, icons and buttons corresponding to functions to be executed by the CPU. Multiple applications may be executed concurrently by the CPU such that each application is associated with one or more windows. Each display element (“pixel”) comprising the display is represented by multiple bits in a computer frame buffer memory coupled to the CPU. An alpha value (&agr;) is associated with the intensity of each pixel of the display, such that multiple images may be blended in accordance with a predefined formula utilizing the alpha values.

Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

Abstract: A graphics system may be configured to render anti-aliased dots in terms of samples and to generate pixels by filtering the samples. The pixels are supplied to one or more display devices. The means used to generate the samples may perform the computation of radial distance at positions on a grid in a rendering coordinate space, and interpolate estimates for the radial distances of samples around the dot as needed based on the radii at the grid positions.

Abstract: A system and method capable of super-sampling and performing super-sample convolution are disclosed. In one embodiment, the system may comprise a graphics processor, a frame buffer, a sample cache, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The frame buffer, which is coupled to the graphics processor, may be configured to store the samples in a sample buffer. The samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the frame buffer, copy the selected samples to a sample cache, and filter a set of the selected samples into an output pixel. The sample-to-pixel calculation unit retains those samples in the sample cache that will be reused in a subsequent pixel calculation and replaces those samples no longer required with new samples for another filter calculation.

Abstract: A system and method are provided for identifying related packets in a communication flow for the purpose of collectively processing them through a protocol stack comprising one or more protocols under which the packets were transmitted. A packet received at a network interface is parsed to retrieve information from one or more protocol headers. A flow key is generated to identify a communication flow that includes the packet, and is stored in a database of flow keys. When the packet is placed in a queue to be transferred to a host computer, the flow key and/or its flow number (e.g., its index into the database) is stored in a separate queue. Near to the time at which the packet is transferred to the host computer, a dynamic packet batching module searches for a packet that is related to the packet being transferred (i.e., is in the same flow) but which will be transferred later in time.

Abstract: A Scheme-1 Termination scheme maximizes system signaling rates by minimizing the signal settling-time when the distance from the middle node to the intersection of the transmission lines is much smaller than the sum of the distances from the end nodes to the intersection of the transmission lines. If the distance from the middle node to the intersection of the transmission lines is not much smaller than the sum of the distances from the end nodes to the intersection of the transmission lines, it has been discovered that a Scheme-2 Termination scheme minimizes the signal settling-time. Alternately, when a Scheme-3 Termination scheme is available, the Scheme-3 Termination scheme maximizes system signaling rates by minimizing the signal settling time when the third transmission line length is more than the second transmission line length divided by two. Otherwise a Scheme-1 Termination scheme minimizes the signal settling time.

Abstract: Authentication and session management can be used with a system architecture that partitions functionality between a human interface device (HID) and a computational service provider such as a server. An authentication manager executing on a server interacts with the HID to validate the user when the user connects to the system via the HID. A session manager executing on a server manages services running on computers providing computational services on behalf of the user. The session manager notifies each service in a session that the user is attached to the system using a given HID. A service can direct display output to the HID while the user is attached to the system. When a user detaches from the system, each of the service's executing for the user is notified via the authentication manager and the session manager. Upon notification that the user is detached from the system, a service can continue to execute while stopping its display to the HID.

Abstract: A computer graphics system that utilizes a super-sampled sample buffer and a sample-to-pixel calculation unit for refreshing the display, wherein the graphics system may store sample position information as offsets to coordinates in the sample buffer. The graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer at computed positions or locations in the sample buffer. The sample positions may be computed using various sample positioning schemes. The sample-to-pixel calculation unit uses the position information to select the samples for filtering during generation of output pixels. In one embodiment, for each sample, the position information comprises one or more offset values, such as an x-offset and a y-offset, wherein the offset values are relative to pre-defined locations in the sample buffer, such as pre-determined pixel center coordinates or predetermined bin coordinates.

Abstract: A method of updating a remote display device associated with a remote system to fill at least a portion of a display area on the display device with a tiled pattern including repetitions of a tile image data stored at a host system interconnected to the remote system via a communication link. The host system determines the number of replications of the tile image data to fill the display area and transmits display information to the remote system via the communication link, including: the tile image data; a number of repetitions of said tile image data to fill said portion of said display area; and coordinate data representing the position of the display area on the display device.

Abstract: An apparatus and method for expediting the processing of requests in a multiprocessor shared memory system. In a multiprocessor shared memory system, requests can be processed in any order provided two rules are followed. First, no request that grants access rights to a processor can be processed before an older request that revokes access rights from the processor. Second, all requests that reference the same cache line are processed in the order in which they arrive. In this manner, requests can be processed out-of-order to allow cache-to-cache transfers to be accelerated. In particular, foreign requests that require a processor to provide data can be processed by that processor before older local requests that are awaiting data. In addition, newer local requests can be processed before older local requests. As a result, the apparatus and method described herein may advantageously increase performance in multiprocessor shared memory systems by reducing latencies associated with a cache consistency protocol.

Abstract: An apparatus for regulating resonance in a micro-chip has been developed. The method includes connecting a de-coupled capacitance across the supply and ground voltages, and connecting a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.

Abstract: Method and system for allowing a computer network operations manager to subscribe for and receive notifications concerning network events from one or more objects or object levels, as defined by distinguished name scoping, and optionally having at least one event characteristic from a selected list. The selected list of characteristics may include: one or more levels of network objects involved in the event; one or more specified network nodes involved in the event; a specified geographical region in which said event occurs; a specified period of days within which the event occurs or is initiated; a specified time interval within which the event occurs or is initiated; a specified class of devices involved in the event; and an event of one or more specified event types.

Abstract: A fan shroud includes a faceplate having slots. Spacer panels and a top plate extend from the faceplate. Hook-like locking features extend from the spacer panels and locking flanges extend from the top plate. To secure a fan in place, the fan shroud is mounted to a rack of a computer system using the hook-like locking features and the locking flanges. The faceplate of the fan shroud is adjacent to and secures the fan in place.