Abstract: The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and methods of coupling semiconductor devices. In a particular embodiment, the semiconductor device is a multi-chip semiconductor that comprises a first semiconductor device and a second semiconductor device. The first semiconductor device has a first surface. The first surface contains a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members. The second semiconductor device has a second surface, the second surface containing a third ridge alignment member, the second semiconductor device positioned such that at least a portion of the third ridge alignment member is located within the receiving area of the first semiconductor device.

Abstract: A method and apparatus for providing a stateless multiplatform instruction set architecture (ISA) for use in a computer system having a processor and memory storing a control program for implementing the invention. The system is used to statelessly execute instructions authored to correspond to a variety of different ISA's on a unitary platform. The ISA of the invention uses a very long instruction word (VLIW) architecture with 64-bit instructions, of which several high-order bits are reserved for an ISA identifier tag. When the processor receives an instruction for execution, it inspects the instruction to determine from the ISA identifier tag to which original, native ISA the instruction corresponds. If the corresponding ISA is the native VLIW ISA for the processor, then the instruction is routed to the instruction dispatch unit of the processor, and thence to at least one functional unit for execution.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A tile array computer is disclosed. A tile array computer is formed by individual tiles, each typically containing a display surface, a processor, memory, and communication devices for providing communications with adjoining tiles or the support structure upon which the tiles are placed.

Abstract: A disk scheduling system with bounded request reordering. Disk access requests may be performed during traversals of a disk head across a disk. Each traversal may have a specified direction of motion. A plurality of disk accesses may be performed during a disk head traversal. The overall number of disk access requests for a given disk head traversal may be limited to a maximum number N. By limiting the number of disk requests for each traversal, a bound may effectively be placed on the amount of time it takes to satisfy any single disk request.

Abstract: A multiprocessor system includes a plurality of central processing units (CPUs) connected to one another by a system bus. Each CPU includes a cache controller to communicate with its cache, and a primary memory controller to communicate with its primary memory. When there is a cache miss in a CPU, the cache controller routes an address request for primary memory directly to the primary memory via the CPU as a speculative request without access the system bus, and also issues the address request to the system bus to facilitate data coherency. The speculative request is queued in the primary memory controller, which in turn retrieves speculative data from a specified primary memory address. The CPU monitors the system bus for a subsequent transaction that requests the specified data in the primary memory. If the subsequent transaction requesting the specified data is a read transaction that corresponds to the speculative address request, the speculative request is validated and becomes non-speculative.

Abstract: A method, in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes, for servicing a memory access request by a first node of the first plurality of nodes. The memory access request pertains to a memory block of a memory module that has a home node different from the first node in the computer network. The home node has a partial directory cache that has fewer directory cache entries than a total number of memory blocks in the memory module. If the memory block is currently cached in the partial directory cache, the first memory access request is serviced using a directory protocol. If the memory block is not currently cached in the partial directory cache, the first memory access request is serviced using a directory-less protocol.

Abstract: The handling of quoted material in an electronic environment is enhanced by using one or more quote bars. Quote bars permit quoted material to be treated as a single object and permit information about the source of a quote to be displayed. They also permit connection to a network address from which a quote may have originated. Using quote bars, the removal of copyright notices can be prevented.

Abstract: A graphics system that is configured to utilize a sample buffer and a plurality of parallel sample-to-pixel calculation units, wherein the sample-pixel calculation units are configured to access different portions of the sample buffer in parallel. The graphics system may include a graphics processor, a sample buffer, and a plurality of sample-to-pixel calculation units. The graphics processor is configured to receive a set of three-dimensional graphics data and render a plurality of samples based on the graphics data. The sample buffer is configured to store the plurality of samples for the sample-to-pixel calculation units, which are configured to receive and filter samples from the sample buffer to create output pixels. Each of the sample-to-pixel calculation units are configured to generate pixels corresponding to a different region of the image. The region may be a vertical or horizontal stripe of the image, or a rectangular portion of the image.

Abstract: A system for collaborating components or objects in a visual development environment is detailed. Collaboration is effected by augmenting eligible components or objects with appropriate collaboration code and registering such components or objects with a server application designated for that purpose which resides on the same HTTP server where the applet that spawned the components to be collaborated also resides. The server application first registers objects or components or portions thereof to be collaborated, builds a record of such links and thereafter interacts with the collaborated components or designated portions thereof to publish, unpublish or update those components and objects, or portions thereof, in accordance with the application server record.

Abstract: A 60 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 60 degree bump placement structures is provided.

Abstract: A circuit and method for generating a write enable pulse that is independent of the clock duty cycle and the clock frequency. The circuit includes a pulse generator for generating a pulse in response to a clock signal and a write enable signal generator for generating a write enable pulse. The pulse tracks the leading edge of the clock signal. A logic circuit is coupled to the pulse generator and the write enable signal generator to generate the write enable pulse by combining the pulse and the write enable signal.

Abstract: A computer graphics system that utilizes a super-sampled sample buffer and a programmable sample-to-pixel calculation unit for refreshing the display, wherein the graphics system may adjust filtering to reduce artifacts or implement display effects. In one embodiment, the graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders a plurality of samples and stores them into a sample buffer. The sample-to-pixel calculation unit reads the samples from the super-sampled sample buffer and filters or convolves the samples into respective output pixels which are then provided to refresh the display. The sample-to-pixel calculation unit may selectively adjust the filtering of stored samples to reduce artifacts, e.g., is operable to selectively adjust the filtering of stored samples in neighboring frames to reduce artifacts between the neighboring frames.

Abstract: A method for constructing a latch mapping between a first level description and a second level description of a digital system, wherein the first level description and the second level descriptions identify components in the digital system using a predefined naming convention, is provided. The method includes identifying first latch components in the first level description and, for each identified first latch component, storing a first string comprising a selected property of the first latch component in a first storage. The method further includes identifying second latch components in the second level description and, for each second latch component, storing a second string comprising a selected property of the second latch component in a second storage. The method further includes generating a latch mapping by matching the first strings in the first storage with the second strings in the second storage.

Abstract: A PC board ejector assembly is provided for disengaging a first PC board from a second PC board in a computer chassis. The PC boards each includes at least one connector for connecting the first PC board to the second PC board. The chassis includes a divider wall. The PC board ejector assembly includes a mounting bracket positioned on at least one of the first and the second PC boards, and a disengagement member coupled to the mounting bracket. The mounting bracket is positioned on the PC board such that movement of the disengagement member engages the member against the divider wall to disengage the PC board connectors from one another and permit removal of at least one of the PC boards. A method for disengaging a PC board including a PC board ejector assembly from a chassis is also provided.

Abstract: A query object generator tool is used to generate interface definitions and source code which implement a database query object. The tool allows a client to construct a query object without being familiar with the underlying database language and without being concerned with programming details such as concurrency problems and connection management. The tool consists of an internal state object which represents the query object, including information which can be saved to reconstruct the query object at a later date, and code generator objects which generate the code required to implement the query object defined by the internal state object. In a preferred embodiment, the code generator objects are arranged in a hierarchy so that a generator object can be instantiated which generator object is specific to the database to be accessed and the language to which the implementation is targeted. An optional graphic user interface (GUI) may also be provided to allow a user to interact with the tool.

Abstract: Embodiments of the invention are used to customize a graphical user interface (GUI) that represents the view in a Model/View/Controller architecture. The model contains an application's data and one or more structural components that are used to identify the GUI components of the view. A factory builds the GUI using characteristics of the structural components to identify a set of GUI components to create the view.

Abstract: A method for including opcode information in an opcode includes numbering the opcode such that a property of the opcode is represented by at least one bit of the opcode. According to one aspect, the number of data units required to advance to the next opcode is encoded into the opcode value itself. According to another aspect, opcodes are numbered such that opcodes having the same properties have opcode values in the same opcode range.

Abstract: A method of selecting a security model for an organization operating an application on the organization's computer network is described. A current strength level for a countermeasure is determined based on input data and rules corresponding to the application. The method and apparatus determine a recommended strength level for countermeasures based on the input data and security risk data. Based on the current strength level and the recommended strength level, the method determines and outputs a security model including a countermeasure and corresponding strength level. The method may also modify the model based on exception conditions. The method may be used to calculate the risk of attack to the application and degree to which the organization conforms to industry practices.

Abstract: Methods and apparatus for a first component to asynchronously invoke a second component are provided. In one embodiment of the invention, a computer-implemented method for a first component to invoke a second component asynchronously in an object-oriented computing environment is provided. A request is received from a first component to invoke a second component. The scope of the received request is maintained. A thread is provided for identifying the received request and invoking the second component, wherein the thread identifies an exception listener for handling exceptions associated with the invocation of the second component.