Abstract: A method and apparatus for dynamic loading of a transport mechanism is provided. A resource locator (RL) corresponding to a collaboration session is requested from a registry. A location indicator to the RL in the registry is received. In response to receiving the location indicator to the RL in the registry, a transportation mechanism specified in the first RL is dynamically loaded, and the collaboration session is joined. Thus, users wishing to collaborate use the registry to determine the type of transport mechanism they need to dynamically load to communicate with each other.

Abstract: A multiprocessing computer system employs local and global address spaces and multiple access modes. A portion of the global memory of the multiprocessing computer system is allocated to each node, called local memory space. Two logical address spaces are mapped to the local memory of each node. A coherent memory replication (CMR) address space stores shadow pages of data from remote nodes and a local address space stores local data. A bit within a local physical address identifies whether data is a shadow page, which is stored in CMR space, or local data, which is stored in local address space. When a transaction requiring a coherency operation is performed, the CMR bit indicates whether a local physical address to global address translation is required. In one embodiment, if the CMR bit is clear, the local physical address is the same as the global address and the local physical address is used for the coherency operation.

Abstract: A method of dynamically switching mapping schemes for cache includes a microprocessor, a first mapping scheme, a second mapping scheme and switching circuitry for switching between the first mapping scheme and the second mapping scheme. The microprocessor is in communication with the cache through the switching circuitry and stores information within the cache using one of the first mapping scheme and second mapping scheme. Also, monitoring circuitry for determining whether one of instructions and load/store operations is using the cache is included. Further, the switching circuitry switches between the first mapping scheme and the second mapping scheme based on which one of instructions and load/store operations is using the cache.

Abstract: In accordance with the present invention a method and system for transmitting multibyte characters in a network comprises the steps, performed by a processor, of receiving a set of fixed-length characters; converting each fixed-length character into a multibyte character to determine a length corresponding to the multibyte characters; and transmitting the length and the multibyte characters.

Abstract: Provided is a method, system, program, and data structure for deriving state information concerning a monitored system component. A status object is provided including information on a current state of the monitored system component. There are a plurality of states associated with the monitored system component, wherein each state is capable of having a state action and at least one transition condition associated with a transition state. A measured system parameter is received and a determination is made as to whether the received measured system parameter satisfies one transition condition associated with the current state indicated in the status object. If the received system parameter satisfies one transition condition, then the state action associated with the transition state associated with the satisfied transition condition is performed. The current state is set to the transition state in the status object.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide a data from a server to a client via a network, where it is determined to send the data to the client, a client information is obtained from the client based on the determination, and after obtaining the client information, the data is sent to the client.

Abstract: The present invention is a technique to minimize crosstalk in multilayer IC packages. According to one or more embodiments of the present invention, signal routing layers are separated by planes for power and ground. Signal trace routing on the routing layers follows either horizontal, vertical or diagonal directions for obtaining high routing densities in the package as is the present design practice. The power and ground planes in one embodiment of the present invention are constructed as a mesh having groups of colinear perforations. The groups are oriented at an arbitrary angle that is chosen to minimize the crossings of groups of signals over mesh openings. It is guaranteed that the number of mesh openings that any given set of three traces encounters is reduced by at least a factor of two. Thus the present invention reduces crosstalk in the package by approximately 50%.

Abstract: A system and method of using refrigerant for cooling electronic components is presented. The system includes a surface. At least one electronic component is coupled to the surface, the at least one electronic component including an integrated circuit. A closed-loop refrigeration circuit is coupled to the surface for removing heat generated by the integrated circuit. The closed-loop refrigeration circuit includes a condenser. A blower is coupled to the surface, the blower having a first port, a second port, and an impeller that rotates around an axis. The blower is oriented such that the axis is perpendicular to the surface and non-intersecting with the condenser, wherein the blower moves air across the condenser.

Abstract: A memory module test system with reduced driver output impedance. A test system includes a plurality of driver circuits, each of which is coupled to a transmission line on a loadboard. The loadboard includes a socket for insertion of the memory module to be tested. A test signal is generated and driven onto a transmission line by a driver circuit. A duplicate test signal is driven by a separate driver circuit onto a separate transmission line. The transmission lines carrying the test signal and duplicate test signal are electrically shorted on the loadboard. Electrically shorting these transmission lines effectively reduces their impedance by half. Multiple test signals generated by the test system are shorted in this manner in order to allow the electrical environment of the test system to more closely approximate that of the application environment of the tested memory module.

Abstract: A method and apparatus for consuming low power when accessing data from a memory array is provided. Further, a method and apparatus for consuming low power when accessing data from a segmented bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells or segments they are in get closer to an output of the segmented bit line structure. Further, a method and apparatus for consuming low power when accessing data from a differential bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells they are in get closer to an output of the differential bit line structure.

Abstract: A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.

Abstract: A device for automatically providing variable resistance includes a comparator for comparing a reference voltage to an operating voltage, a first switch operatively coupled to the comparator, a first resistor operatively coupled with the first switch in a series connection between a pull-up voltage and a signal line, a second switch operatively coupled to the comparator, and a second resistor operatively coupled in a series connection with the second switch between the pull-up voltage and the signal line. The first switch selectively electrically enables the connection between the pull-up voltage and the signal line through the first resistor based on the comparison between the reference voltage and the operating voltage and the second switch selectively electrically enables the connection between the pull-up voltage and the signal line through the second resistor based on the comparison between the reference voltage and operating voltage.

Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer. The pair of parallel planar conductors includes a first power supply plane suitable for use, for example, as a ground plane and a second power supply plane suitable for use, for example, as a power plane (e.g., VCC). The dielectric layer has a loss tangent value of at least 0.2, and preferably of at least 0.3. In one embodiment, the dielectric material between the power planes could have a frequency dependent loss tangent, such that a loss tangent value of 0.3 is achieved at and above the lowest resonance frequency of the planes.

Abstract: A circuit for regulating resonance in a micro-chip has been developed. The circuit includes micro-chip supply voltage and a ground voltage, and a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.

Abstract: A method for dividing a high frequency clock signal for analysis of all clock edges has been developed. The method includes receiving a high frequency clock signal and dividing it up into multiple phases that represent respective edges of the clock signal. The initial phases are generated by the divider with each subsequent phase lagging its preceding phase by one clock cycle. Additional subsequent phases are generated by inverting corresponding initial phases.

Abstract: A high density, high speed, and low power circuit scheme is presented for vector switching port applications for advanced IC design. Embodiments exhibit superior area-delay-power properties. The technique benefits a wide range of product applications ranging from high speed high bandwidth router to low power portable computing hardware. 5.0 TBPS peak traffic can be supported for an on-chip vector port.

Abstract: The health of a process is monitored in a computer system by a process monitor. The monitored process (a configuration management system daemon (CMSD)) is not a child of the process monitor. The process monitor uniquely determines the identity of a monitored process and verifies the correct operation of the monitored process. In the absence of verification of the correct operation of the monitored process, the monitored process is caused to initiate. On successful initiation of the monitored process, the monitored process is uniquely identified to the system and is detached from the process monitor. Each monitored process is arranged to write, on initiation, its unique process identification information (PID) to a file, which file is then accessed by the process monitor to identify the process monitor. The process monitor can interrogate the operating system to verify correct operation of the CMSD.

Abstract: Techniques for indicating partial fullness levels of a FIFO comprising a plurality of stages using a partial fullness detector, such as a m-out-of-n detector. According to an embodiment, the m-out-of-n detector is coupled to “n” stages of the FIFO and configured to output a partial fullness indicator signal based on the full/empty states of the stages coupled to the m-out-of-n detector. The m-out-of-n detector may be configured to output the partial fullness indicator signal in a first state when “m” stages coupled to the m-out-of-n detector are full, and to output the partial fullness indicator signal in a second state when “m” stages coupled to the m-out-of-n detector are empty. The number of full stages of the FIFO lies in a first range when the m-out-of-n detector outputs the signal in the first state, and in a second range when the m-out-of-n detector outputs the signal in the second state.

Abstract: A user selects base text from a working document for which ruby text is desired. The base text is displayed in a ruby handling window. Despite the ruby handling window being open, the user can change focus to the working document, perform normal operations in the working document, such as text editing or may even change the selection of the base text. Such an amendment of the selected base text is then directly updated in the ruby handling window based on the newly selected base text.

Abstract: The invention relates to methods and apparatus for accessing data that is periodically transmitted by a broadcaster. In accordance with one aspect of the invention, a receiver capable of reception of data is disclosed. The data is transmitted by a broadcaster in a broadcasting system. The receiver reduces the delay conventionally encountered in accessing periodically transmitted data in a broadcasting system.