Abstract: A test breakout board using blind vias to eliminate stubs. The test breakout board includes a printed circuit board (PCB), having a first set of contact pads on one side and a second set of contact pads which are directly opposite the first set of contact pads on it's other side. Each pad in the first set of contact pads is connected to a corresponding pad in the second set of contact pads through a pair of blind vias, a pair of signal traces and a through-hole via. Each of the through-hole vias is connected to a corresponding contact pin in a test connector. The test connector provides an interface to test equipment such as a logic analyzer or an oscilloscope. The test breakout board may include a test socket for holding a device-under-test (DUT), such as a microprocessor or an application specific integrated circuit (ASIC) chip. Additionally, the breakout board may also include an electrical interface adapter, which mechanically resembles the DUT.

Abstract: A circuit for reducing the noise associated with a clock signal for a flip-flop based circuit has been developed. The circuit includes a charge control portion that stores charge at a pre-determined time of the clock cycle and a dump control portion that releases the stored current also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal.

Abstract: A parallel filesystem remote access subsystem facilitates remote access to files in a parallel filesystem in a digital computer network, the network including at least one client computer and a plurality of server computers interconnected by a communication link, and each server computer storing a portion of at least one file in the parallel filesystem. The parallel filesystem remote access subsystem includes, associated with the server computer, a parallel filesystem input/output daemon, and, associated with the client computer, a parallel filesystem module and a parallel filesystem proxy daemon. The parallel filesystem module receives access requests generated to access a file in the parallel filesystem and refer the access requests to the parallel filesystem proxy daemon, and the parallel filesystem proxy daemon, in turn, generates server access request messages for transfer over the communications link.

Abstract: A method for including opcode information in an opcode includes numbering the opcode such that a property of the opcode is represented by at least one bit of the opcode. According to one aspect, the number of data units required to advance to the next opcode is encoded into the opcode value itself. According to another aspect, opcodes are numbered such that opcodes having the same properties have opcode values in the same opcode range.

Abstract: An integrated circuit device including an integrated circuit die having at least a first and a second heat-generating components formed thereon, and a heat dissipation structure thermally coupled to the die to dissipate heat generated by the components. The heat dissipating characteristics of the heat dissipation structure are tailored to match the heat generated by each of the first and second components.

Abstract: Where it is desired to perform a double precision operation using single precision operands, first and second single precision operands are loaded into first and second respective rows of a re-order buffer, and third and fourth single precision operands are loaded into third and fourth respective rows of the re-order buffer. A first merge instruction copies the first and second single precision operands from respective first and second rows of the re-order buffer into first and second portions of a fifth row of the re-order buffer, thereby concatenating the first and second single precision operands to represent a first double precision operand. A second merge instruction copies the third and fourth single precision operands from respective third and fourth rows of the re-order buffer into first and second portions of a sixth row of the re-order buffer, thereby concatenating the third and fourth single precision operands to represent a second double precision operand.

Abstract: One embodiment of the present invention provides a system that facilitates multi-dimensional space and time dimensional execution of computer programs. The system includes a head thread that executes program instructions and a series of speculative threads that execute program instructions in advance of the head thread, wherein each speculative thread executes program instructions in advance of preceding speculative threads in the series. The head thread accesses a primary version of the memory element and the series of speculative threads access space-time dimensioned versions of the memory element. The system starts by receiving a memory access to the memory element. If the memory access is a write operation by the head thread or a speculative thread, the system determines if a version of the memory element associated with the head thread or speculative thread exists. If not, the system creates a version of the memory element for the thread.

Abstract: A method of inserting repeaters into a complex integrated circuit includes the step of selecting, based upon signal transition data, a maximum wire length to be positioned between two repeaters in a complex integrated circuit. The maximum wire length is then correlated with a signal transition-based ratio coefficient defining the relation between a signal transition time and a Resistive-Capacitive delay. A signal transition-based Resistive-Capacitive delay is then defined based upon the signal transition-based ratio coefficient. A repeater distribution is then mapped within the complex integrated circuit based upon the signal transition-based Resistive-Capacitive delay.

Abstract: In a distributed computing system, a first process may register interest in an event occurring in another address space or physical machine in such a way as to allow the subsequent notification of the event's occurrence to contain an object that includes methods that are to be run on receipt of the notification. When the notification is received, either by the first process or by some other entity designated by the first process to be the final point of notification, the methods may be executed as specified by the first process.

Abstract: A method for transacting business electronically includes storing first information in a database management module, reading the first information in the database management module by a network server module, providing a client customized interface with the first information by the network server module, providing client information and product information to a file transfer module responsive to a client ordering a product, and transferring a product to a client by the file transfer module.

Abstract: A method and system for evaluating a set of credentials that includes at least one group credential and that may include one or more additional credentials. A trust rating is provided in association with the at least one group credential within the set of credentials and trust ratings may also be provided in other credentials within the set of credentials. Each trust rating provides an indication of the level of confidence in the information being certified in the respective credential. In response to a request for access to a resource or service, an evaluation of the group credentials is performed by an access control program to determine whether access to the requested resource or service should be provided. In one embodiment, within any given certification path a composite trust rating for the respective path is determined. An overall trust rating for the set of credentials is determined based upon the composite trust ratings.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention produce a three-dimensional rotational image from a two-dimensional image including a plurality of objects. Each object is assigned to one of a plurality of sequential layers that correspond to visually depicted depths of the objects in the two-dimensional image. The objects are rotatively displayed to produce the three-dimensional rotational image.

Abstract: Method and apparatus for simultaneous optimization of the compiler to generate codes that may be compatible and acceptable for two or more different processors without potentially sacrificing the performance on any processors is provided. In particular, the rules of instructions scheduling for the machines of interest of different processors are abstracted. From the abstractions, a hypothetical machine is generated that is the restrictive or constraining set of the actual machines modeled in the abstraction step. After generating the hypothetical machine, the restricted hypothetical machine is targeted rather than the actual machines modeled in the first step. Thereafter, conflicts, if any are resolved by modeling the performance impact and selecting the less damaging choice.

Abstract: A system and method for automatically selecting decoupling capacitors for an electronic device. The system determines a localized drive strength for each component in the electronic device. Based on a summation of drive strengths for components in a given area of the electronic device, the system determines whether a decoupling capacitor is necessary to provide local power bus stability.

Abstract: A method and apparatus for retaining a component within a base structure is provided. The component retention mechanism, in accordance with one example embodiment of the present invention, has a bolt receiver mounted to a base structure into which the component to be installed mounts. The base structure can be, e.g., a computer hardware rack structure. A spring casing mounts to the component to be installed. A spring having a first end and a second end mounts within the spring casing. At least one bolt extends from one of the first and second ends of the spring, such that the bolt engages with the bolt receiver to retain the component in the base structure as desired.

Abstract: A test stand for testing computer hardware components is provided. The test stand has a base structure. A first support arm mounts to the base structure. The first support arm has one or more apertures disposed therein to enable airflow through the support arm to avoid airflow hindrance of cooling fans during operation of the subject internal computer hardware components and when the test stand is in certain positions. A second support arm also mounts to the base structure. The second support arm has a rotation mechanism mounted therein. A support bracket for supporting the test subject computer hardware components extends between the first support arm and the second support arm. The support bracket is in communication with the rotation mechanism, such that the rotation mechanism controls and enables the rotation of the support bracket through a predetermined rotational degree range.

Abstract: A system dynamically generates interfaces on demand during runtime execution of an application containing a plurality of objects. A user object generates a request for an interface of a service object. The service object, if the interface is not available, generates an adapter request and transmits same to an adapter manager. The adapter manager selects an interface adapter based on the adapter request from a library of interface adapters or aggregates a composite adapter and transmits the obtained interface adapter to the service object. The service object enables access from the user object based on the received interface adapter.

Abstract: A method and apparatus for embedding of bytecode data in a transport stream is described. Embodiments of the invention serve to make Java™ bytecode (in a class file) concurrently available to a user that is receiving media information through a transport stream. To ensure the concurrent delivery of bytecode, the information is embedded within spaces allocated in the transport stream, or in packets that carry the media data. In one embodiment of the invention, media data is grouped in structured packets referred to as Packetized Elementary Stream (PES) packets. Predefined spaces are available in each PES packet where bytecode data is embedded. In one embodiment of the invention the pre-defined space is allocated within the header segment of a PES packet. In another embodiment bytecode instruction are embedded within a private stream segment of a PES packet. One transport stream used with the invention is an MPEG-2 transport stream that includes structured packets that transport the PES packets.

Abstract: One embodiment provides for a system that uses a time stamp in order to more efficiently mark objects to keep track of accesses to fields with the objects. Upon receiving a first reference to a first field in an object, the system determines whether the first field has been accessed within a current time period. The system does so by retrieving a time stamp associated with the object. This time stamp indicates the last time any marking bit associated with any field in the object was updated. The system compares the time stamp with a current time value associated with the current time period. The system additionally retrieves a first marking bit associated with the first field and determines if the first marking bit is set. If the first marking bit is set and if the time stamp equals the current time value, the system determines that the first field has been accessed in the current time period.

Abstract: A graphics system configured to perform programmable filtering of samples to generate pixel values. The graphics system comprises a frame buffer, an accelerator unit and a video output processor. The accelerator unit receives graphics primitives, renders samples for the graphics primitives, and stores the rendered samples into a sample area of the frame buffer. The accelerator unit subsequently reads the samples from the sample area of the frame buffer, and filters the samples with a programmable filter having a programmable support region. The resulting pixel values are stored in a pixel area of the frame buffer. The video output processor reads the pixel values from the pixel area and converts the pixel values into a video signal which is provided to a video output port.