Abstract: Providing a resource domain structure allows flexible management of resources. With flexible management, computations, such as threads and processes, do not have to be related to be bound to the same resource domain. Since resource domains do not require the parent-child relationship, unrelated computations can bind each other to their resource domains. A data structure identifies a resource domain, the resource of the domain, and implementation of a resource management policy. The implementation of the resource management policy includes policy action, which when executed invoke policy imposing isolates. The resource domain data structure also indicates availability of usage of the resource.

Abstract: A mechanism for dynamically performing Network Address Translation that allows external devices to contact internal host systems that would otherwise be hidden behind a NAT device is discussed. The dynamic NAT mechanism of the present invention maps internal host system addresses to external network addresses and reconfigures the NAT configuration of the network firewall to account for the new mapping on demand. Domain Name Service (DNS) lookup requests for an authorized internal system serve as a trigger to create a new mapping between the internal host system and the external network address. The new mappings may have a lifecycle controlled by dynamic leases that are created for each new mapping.

Abstract: A system including a network interface card (NIC) associated with a Media Access Control (MAC) address and a host operatively connected to the NIC. The NIC includes a default hardware receive ring (HRR), a plurality of non-default HRRs, and a hardware classifier. The hardware classifier is configured to analyze an inbound packet using a destination Internet Protocol (IP) address and to send the inbound packet to one of the plurality of non-default HRRs if the inbound packet is a unicast packet, and to send the packet to the default HRR if the inbound packet is an inbound multi-recipient packet. The host includes a plurality of virtual NICs (VNICs) and an inbound software classifier, that includes a plurality of software receive rings (SRRs) and is configured to obtain inbound packets from the default HRR, and to determine to which of the plurality of SRRs to send a copy of the packet.

Abstract: A system and method for selectively replacing standard threshold voltage devices with low threshold voltage devices in a digital logic design. The system identifies at least one path having a first timing value, the path having a plurality of standard threshold devices. The path is reverse traversed, or otherwise analyzed or traversed, to identify at least one of the standard threshold devices to possibly replace with a corresponding low threshold device. The system also determines a timing value for the path associated with replacing the at least one standard threshold device with the corresponding low threshold device. Depending the analysis, the standard threshold device may be replaced with a low threshold device, such as when the path timing improves by replacement. Such replacement may be used in various paths, such as paths considered critical paths in a digital logic design.

Abstract: A meeting facilitation tool may perform and/or facilitate the planning, scheduling, holding, and/or following up of meeting related activities. A meeting facilitation tool may schedule a meeting time by interacting with meeting participants to determine a time range during which all the participants are available. Additionally, a meeting facilitation tool may programmatically interact with calendar data to schedule the meeting with each participant. A meeting facilitation tool may also allow reviewing of information for previous meetings. Additionally, a meeting facilitation tool may configure and/or initiate teleconferencing or video conferencing as well as the audio and/or video recording of the meeting. A meeting facilitation tool may also track and completion of action items assigned during a meeting.

Abstract: A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced leakage adjustment control (ILAC). The LSDC includes a combination of PMOS transistors, NMOS transistors or both PMOS and NMOS transistors that are controlled by a plurality of stress inducing signals. The PMOS and/or NMOS transistors of the LSDC are coupled to a pair of complementary data lines. The complementary data lines are inputs to a sense amplifier and are outputs of a write driver. The ILAC controls the quantity of the leakage stress applied through the LSDC to the pair of complementary data lines. The ILAC further includes a leakage varying circuitry that is configured to adjust the leakage stress applied to the complementary data lines through the LSDC.

Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms and define aspects of an instruction set architecture consistent therewith.

Abstract: A semiconductor device includes a stored device identifier that is accessible to external systems, and a stored secret key that is inaccessible to external systems. The device also includes an input, which in operation receives a system identifier, representing the system into which the device is to be incorporated, and an authorization key. An authorization unit within the device is then used for enabling or disabling the device in accordance with the values of the stored secret key, the received system identifier and the authorization key. The authorization key is typically supplied by a support center in response to being notified of the device identifier. In one embodiment, the authorization unit encrypts the system identifier using the stored secret key as the encryption key and then compares the result against the authorization key.

Abstract: A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected to a low power supply and a high power supply and has two states of operation: a write operation state and a read operation state. For each state of operation, the voltage level switch selectively provides a power supply if a column has been selected or if the operation is a read or write. The recycle charge storage stores excess charge from SRAM cells after a read operation or after a write operation in unselected columns. After the read or write operation, the recycle charge storage discharges excess charge to the bitlines during bitline precharging.

Abstract: A method of managing nested monitor locks in a computer program is provided for an application having at least a first thread and a second thread wherein a non-synchronized procedure is processed by the application. The first thread executes an outer software module while the second thread executes an inner software module. A processing state of the second thread code is preserved before the second thread is configured to release an outer monitor of the outer software module. The first thread acquires the outer monitor of the outer software module so that actions may be completed. Upon completion of actions by the first thread, the outer monitor of the outer software module is released. The processing state of the second thread is restored, such that, actions of the second thread are allowed to be completed.

Abstract: One embodiment of the present invention provides a system that facilitates locked prefetch scheduling in general cyclic regions of a computer program. The system operates by first receiving a source code for the computer program and compiling the source code into intermediate code. The system then performs a trace detection on the intermediate code. Next, the system inserts prefetch instructions and corresponding locks into the intermediate code. Finally, the system generates executable code from the intermediate code, wherein a lock for a given prefetch instruction prevents subsequent prefetches from being issued until the data value returns for the given prefetch instruction.

Abstract: A communications chip having a plurality of ports. Each port is provided with an interface for attachment to an external communications facility to exchange data traffic. There is also a switching matrix for routing data traffic on the chip between the ports. The chip further includes a plurality of logic analyzers. Each logic analyzer is associated with a corresponding one of the ports. Each logic analyzers is operable to monitor data traffic passing through its corresponding port and to trigger on one or more predetermined conditions relating to the monitored data traffic. The chip further includes a control interface to allow reconfiguration of the predetermined conditions for at least one of the logic analyzers.

Abstract: Many conventional lock-free data structures exploit techniques that are possible only because state-of-the-art 64-bit processors are still running 32-bit operating systems and applications. As software catches up to hardware, “64-bit-clean” lock-free data structures, which cannot use such techniques, are needed. We present several 64-bit-clean lock-free implementations: including load-linked/store conditional variables of arbitrary size, a FIFO queue, and a freelist. In addition to being portable to 64-bit software (or more generally full-architectural-width pointer operations), our implementations also improve on existing techniques in that they are (or can be) space-adaptive and do not require a priori knowledge of the number of threads that will access them.

Abstract: Method and apparatus for programmatically generating interesting audio file playlists. A playlist generation mechanism may use an N-gram model of audio file ordering patterns found in a collection of human-generated playlists to automatically generate new playlists. Given play histories indicating one or more played audio files as input, statistical methods may be used to look for sequences of audio files that occur a statistically significant number of times in the N-gram model for inclusion in new, interesting playlists that incorporate the human element found in the collection of playlists. In some embodiments, one more backoff probability methods may be used to provide additional candidate audio files for playlists if there is insufficient coverage for an audio file in the N-gram model. In one embodiment, a class-based statistical model incorporating higher-level statistics for the audio files may be used to weight selection of audio file transitions from the N-gram model.

Abstract: Reference architecture instructions are translated into target architecture operations. In some embodiments, an execution unit of a processor executes a function determined from a collection of operations, the function specifying functionality based on instructions, the collection selected from operations translated from the instructions. In further embodiments, the function is specified as a fused operation. Sequences of operations are optimized by fusing collections of operations; fused operations specify a same observable function as respective collections, but advantageously enable more efficient processing. In some embodiments, a collection comprises multiple register operations. Sequences of operations, in a predicted execution order in some embodiments, form traces. In some embodiments, fusing operations requires setting only final architectural state, such as final flag state; intermediate architectural state is used implicitly in a fused operation.

Abstract: One embodiment of the present invention provides a system that performs a real-time root-cause-analysis for a degradation event associated with a component under test. During operation, the system monitors a telemetry signal collected from the component, and while doing so, attempts to detect an anomaly in the telemetry signal. If an anomaly is detected in the telemetry signal, the system performs a failure analysis on the telemetry signal in real-time while the telemetry signal is degrading. Next, the system identifies a failure mechanism for the component based on the failure analysis.

Abstract: A liquid cooled rack with compliant heat exchanger support structure includes a rack having a rigid frame for supporting electronic components therein, a plurality of flexible supports connected to the rigid frame, and a liquid-fed heat exchanger mounted within the rack via the plurality of flexible supports. The plurality of flexible supports are connected to the heat exchanger and configured to flexibly support the liquid-fed heat exchanger with respect to the rigid frame.

Abstract: A method for optimizing executable code includes identifying a plurality of instructions in the executable code matching a predetermined instruction pattern, assessing whether the binary number conforms to a predetermined bit pattern, and transforming the plurality of instructions into transformed instructions when the binary number conforms to the bit pattern.

Abstract: A tape drive for reading both new technology tapes and legacy tapes. The tape drive includes a three bump head with two outer read bumps and an inner write bump. The outer read bumps include readers for reading data from tracks of a first width on a first storage tape while the inner write bump includes writers for writing data in tracks of the first storage tape. Legacy readers are provided in the head to read data from tracks of a second width that is greater than the first track width on a second storage tape. The legacy readers are provided by piggybacking or merged-pole techniques in the inner write bump or are provided in one or both of the outer read bumps. The tape drive includes control circuitry with channels for processing data signals from the narrower readers and channels for processing data signals from the wider legacy readers.

Abstract: A method for gathering management information about an asset that includes receiving a first request for the management information about the asset, wherein the first request complies with the information model format, identifying a data acquisition (DAQ) definition for the DAQ definition complies with the DAQ format, triggering a protocol handler according to the DAQ definition, receiving the management information from the protocol handler about the asset, and updating a cache entry with the management information.