Abstract: An ejector latch for removing a blade module from a server chassis includes a latch lever, an ejector catch, and an ejector pull part. The latch lever includes a pivot hole near a first end thereof operable to be coupled to the blade module and a bend near a second end thereof. The ejector catch includes a through-hole passing therethrough and a hook operable to hook onto the server chassis. The ejector pull part includes an integrated spring operable to return the ejector pull part to an original position after being pulled. The second end of the latch lever passes through the through-hole of the ejector catch. The ejector pull part is disposed on the bend near the second end of the latch lever and inside the through-hole of the ejector catch such that, when the ejector pull part is pulled, the ejector pull part slides along the bend near the second end of the latch lever and pushes on a wall of the through-hole to disengage the hook of the ejector catch from the server chassis.

Abstract: A method for executing an application on a plurality of nodes, that includes synchronizing a first clock of a first node of the plurality of nodes and a second clock of a second node of the plurality of nodes, configuring a first hypervisor on the first node to execute a first application domain and a first privileged domain, wherein configuring the hypervisor comprises allocating a first number of cycles of the first clock to the first privileged domain, configuring a second hypervisor on the second node to execute a second application domain and a second privileged domain, wherein configuring the second hypervisor that includes allocating the first number of cycles of the first clock to the second privileged domain, and executing the application in the first application domain and the second application domain, wherein the first application domain and the second application domain execute semi-synchronously and the first privileged domain and the second privileged domain execute semi-synchronously.

Abstract: A method for installing a device driver for a device in a guest domain, that includes obtaining a first device driver for the device by a hypervisor, installing, by the hypervisor, the first device driver into memory allocated to the guest domain, and notifying an operating system in the guest domain of the first device driver after installing the device driver, wherein the operating system communicates with the device using the first device driver.

Abstract: A kernel data transfer method and system for transmitting multiple packets of data in a single block of data presented by application programs to the kernel's network subsystem for processing in accordance with data transfer parameters set by the application program. The multi-packet transmit system includes logic that allows header information of the multiple packets of data to be generated in a single buffer and appended to a second buffer containing the data packets to be transmitted through the network stack. The multi-data transmit system allows a device driver to amortize the input/output memory management related overhead across a number of packets. With some assistance from the network stack, the device driver needs to only perform the necessary IOMMU operations on two contiguous memory blocks representing the header information and the data payload of multiple packets during each transmit call.

Abstract: A movable data center is disclosed that comprises a movable enclosure having partitions that define a closed-loop air flow path. A plurality of fans and a plurality of data processing modules are disposed in the air flow path. A pipe network is disposed within the enclosure that includes a chilled water supply pipe that receives chilled water from a source of chilled water. A water return pipe is provided that circulates water back to the source of chilled water. A plurality of heat exchange modules is installed in the enclosure in the air flow path. The heat exchange modules receive the chilled water from the chilled water supply pipe. Each of the heat exchange modules has a water circulation tube that connects the chilled water supply pipe to the return water pipe.

Abstract: Mechanisms and processes for synchronizing a group of threads that use a semaphore for each waiting thread to implement a barrier. A barrier is created comprising a counter, a semaphore list, and at least one mutual exclusion (mutex) lock. For each thread using the barrier, it is determined whether that thread is the last to arrive. For each thread that is not the last to arrive at the barrier, the thread is caused to wait on a semaphore. The last thread to arrive at the barrier causes each waiting thread to resume execution.

Abstract: A method and apparatus for digital content access control comprises determining the occurrence of a synchronization event that triggers synchronization of information used by one or more content provisioners to create an authenticated digital content request that is based at least in part on a digital content request comprising a request for digital content with information used by one or more content repositories to validate the authenticated digital content request and to return the digital content based at least in part on the validation. The method also comprises determining the information in response to the sychronization event and sending the information to at least one of the group comprising the one or more content provisioners and the one or more content repositories.

Abstract: A flow manager may receive packet flow rules from one or more network services and may generate a unified rule set according to the received packet flow rules. A flow manager may additionally split the unified rule set into subsets for enforcement by one or more flow enforcement devices and may install the rule subsets onto the flow enforcement devices. When splitting the unified rule set into subsets, a flow manager may analyze a network topology connecting the flow enforcement devices. A flow manager may also receive additional packet flow rules, integrate them into the unified rule set, update the rule subsets according to the additional rules, and install the updated subsets onto the flow enforcement devices.

Abstract: An infrastructure is provided for creating applications for mobile information devices, using a tag-based markup language, MIDML. Applications are defined based on easily manipulated textual tags, without need for writing specific code. The tags are processed to ultimately generate source code files. Initially, the input is parsed. Next, a hierarchical object model of the application is populated with objects. Separate readers read and parse the different tags and accompanying elements. The readers are registered in a descriptor object factory, to be instantiated as required in processing extended MIDML files. The object model enables the capabilities of the system to be easily extended, simply by adding new tags, and readers to the existing factory set. The resulting object model is accessible to a generator that produces the actual output.

Abstract: A server interconnect system for sending data includes a first server node and a second server node. Each server node is operable to send and receive data. The interconnect system also includes a first and second interface unit. The first interface unit is in communication with the first server node and has one or more RDMA doorbell registers. Similarly, the second interface unit is in communication with the second server node and has one or more RDMA doorbell registers. The system also includes a communication switch that is operable to receive and route data from the first or second server nodes using a RDMA read and/or an RDMA write when either of the first or second RDMA doorbell registers indicates that data is ready to be sent or received.

Abstract: In one embodiment, a memory controller for a node in a multi-node computer system comprises logic and a control unit. The logic is configured to determine if an address corresponding to a request received by the memory controller on an intranode interconnect is a remote address or a local address. A first portion of the memory in the node is allocated to store copies of remote data and a remaining portion stores local data. The control unit is configured to write writeback data to a location in the first portion. The writeback data corresponds to a writeback request from the intranode interconnect that has an associated remote address detected by the logic. The control unit is configured to determine the location responsive to the associated remote address and one or more indicators that identify the first portion in the memory.

Abstract: One embodiment of the present invention facilitates favoring the performance of a single-threaded application in a computer system that supports simultaneous multi-threading (SMT), wherein multiple threads of execution simultaneously execute in an interleaved manner on functional units within a processor. During operation, the system maintains a priority for each simultaneously executing thread. The system uses these priorities in allocating a shared computational resource between the simultaneously executing threads, so that a thread with a higher priority is given preferential access to the shared computational resource. This asymmetric treatment of the threads enables+ the system to favor the performance of a single-threaded application while performing simultaneous multi-threading.

Abstract: In accordance with the present invention a process is provided for allocating and deallocating resources in a distributed processing system having a requester platform and a server platform. The process involves receiving a request from the requestor platform referring to a system resource and specifying a requested lease period, permitting shared access to the system resource for a lease period, sending a return call to the requestor platform advising of the lease period, and deallocating the system resource when the lease period expires.

Abstract: A method for performing application and task discovery in a network of computer devices. The method includes broadcasting a request for application data, such as a multicast request, over a communications network. Responses are received from agents on the computer devices and include application data such as an application name or identifier and an application launch point. A list of tasks that each application can run is also typically included in the application data, and associated with each task is a task entry point and a list of elements the task can be run against. Additional element information may be provided for each application including a list of elements managed by each application. The method continues with generating link and launch lists for the network such as a list that includes task identifiers with task entry points or a list that provides application names with launch points.

Abstract: A system for displaying a user interface for a telematics client is provided. The system includes a display panel configured to display image data and a graphics processor in communication with the display panel. A draw manager in communication with the graphics card is included. An application buffer in communication with the draw manager is provided. The application buffer configured to receive the image data from an application. The application buffer is further configured to transmit the image data to the draw manager at a first rate. The draw manager is configured to determine a rate of updating an object of the display image through manipulation of the image data received from the application buffer. A draw manager and method for providing efficient updates for a display screen associated with a telematics system are included.

Abstract: A computerized device having a first processing device, a second processing device, and an interconnection mechanism allowing communication between the first and second processing devices, provides a mechanism for testing a processing device by performing the isolation and testing operations of operating the first processing device in a normal processing mode and transitioning the first processing device from the normal processing mode to an isolated processing mode. The device performs a test process on the first processing device while in isolated processing mode to test functional portions of the first processing device. If operation of the test process produces an error in a functional portion of the first processing device, the test process notifies a control process on a second processing device of the error in the functional portion of the first processing device in which the test process produced an error.

Abstract: Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue.

Abstract: An elliptic curve processing apparatus that performs operations on elliptic curves specified over binary polynomial fields includes a functional unit that has a digit serial multiplier with a digit size of at least two bits. The elliptic curve processing apparatus performs reduction for respective generic curves using arbitrary irreducible polynomials, which correspond to respective ones of the generic curves. The elliptic curve processing apparatus may include hardwired reduction circuits in the functional unit for use with respective named curves. A storage location in the elliptic curve processing apparatus may be used to specify whether an operation is for one of the named curves or for one of the generic curves.

Abstract: An apparatus and method for efficiently managing data cache load misses is described in connection with a multithreaded, pipelined multiprocessor chip. A CMT processor keeps track of load misses for each thread by issuing a load miss signal each time a load instruction to the data cache misses. A detection logic functionality in the IFU responds the load miss signal to determine if a valid instruction from the thread is at the one of the pipeline stages. If no instructions from the thread are detected in the pipeline, then no flush is required and the thread is placed in a wait state until the requested data is returned from higher order memory. If any instruction from the thread is detected in the pipeline, the thread is flushed and the instruction is re-fetched.

Abstract: A method and apparatus for creating virtual worlds wherein a user may begin with a database containing a limited pictorial representation of a desired virtual world and then edit the database to specify the remaining data needed to create the actual virtual world. In one embodiment of the present invention, a database containing a limited pictorial representation of a virtual world is communicated to a receiving unit, and a grouping unit collects various descriptions of the pictorial representation into selected groups. An attribute assigning unit then assigns attributes to the groups. The attributes may include group hierarchy, constraints of motion, color, texture or other features. The modified database is then communicated to a data coupling unit which couples real world data to the groups. Finally, a rendering unit renders the virtual world which looks and functions according to the specified attributes and the real world data.