Abstract: A method and apparatus for controlling power consumption in a multi-threaded processor. In one embodiment, the processor includes at least one logic unit for processing instructions. The logic unit includes a plurality of positions, wherein each of the plurality of positions corresponds to at least one instruction thread. Clock signals may be provided to the logic unit via a clock gating unit. The clock gating unit is configured to inhibit a clock signal from being provided to a corresponding one of the thread positions when no instruction thread is active for that position. The inhibiting of the clock signal for an inactive thread position may reduce power consumption by the processor.

Abstract: A computer system configured to enhance data protection. A computer system includes one or more clients, such as processing subsystems and a memory subsystem interconnected via a network. Transactions within the system may involve the separation of data and a corresponding address in both space and time. At various points in the system, operations may be performed which seek to reunite a data and corresponding address, such as a store operation. In order to further ensure the correspondence of data and an address which is to be used in an operation, clients are configured to generate and utilize an additional symbol. The symbol is generated at least in part on an address which corresponds to data. The symbol is then associated with the data and serves to represent the corresponding address. The symbol may then be utilized by various clients within the system to check an address which is proposed to be used in an operation with the data.

Abstract: Techniques, systems, and apparatus for conducting direct data placement of network message data to a final destination in a user buffer are disclosed. Generally, the invention is configured to conduct direct data copying from a NIC memory to a final destination user buffer location without any intermediate copying to a kernel buffer. The invention includes a method that involves receiving network delivered messages by a NIC of a local computer. The message is stored in the memory of the NIC. The headers are stripped from the message and processed. A ULP handler of the local computer is invoked to process the ULP header of the network message. Using information obtained from the processed ULP header, suitable memory locations in a user buffer are identified and designated for saving associated message data. The message data is then directly placed from the NIC memory to the designated memory location in the user buffer without intermediate copy steps like DMA.

Abstract: One embodiment of the present invention provides a system that facilitates detecting an anomaly in a signal, wherein the signal is sampled to produce a set of possible quantized signal values. During operation, the system constructs a “reference distribution” for an “occurrence frequency” of a specific quantized signal value from the set of possible quantized signal values. The system then obtains a “deviant distribution” associated with the reference distribution, wherein the deviant distribution has an offset from the reference distribution to indicate an anomaly in the signal. Next, in response to a new occurrence of the specific quantized signal value, the system updates a mean and a variance of the reference distribution for the specific quantized signal value. The system also adjusts the deviant distribution for the specific quantized signal value based on the updated mean and the updated variance of the reference distribution for the specific quantized signal value.

Abstract: One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution mode, the system receives an invalidation signal for a cache line at the L1 cache wherein the invalidation signal is received from a cache-coherence system within the multiprocessor. In response to the invalidation signal, if the cache line exists in the L1 cache, the system examines a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during speculative execution. If the load-mark is set, the system fails the speculative-execution mode and resumes a normal-execution mode from a checkpoint.

Abstract: A message brokering mechanism for a transaction processing system may include first and second stages operable to exchange message requests and responses. The first stage may be operable to receive a message request from a message source and to check whether there is an existing first stage response to the message request. In some embodiments, if there is an existing first stage response, the first stage may dispatch the existing first stage response to the message source.

Abstract: One embodiment of the present invention provides a system that non-intrusively detects counterfeit components in a target computer system. During operation, the system collects target electromagnetic interference (EMI) signals generated by the target computer system using one or more antennas positioned in close proximity to the target computer system. The system then generates a target EMI fingerprint for the target computer system from the target EMI signals. Next, the system compares the target EMI fingerprint against a reference EMI fingerprint to determine whether the target computer system contains a counterfeit component.

Abstract: A system and method for verifying the transmit path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., hosts, input buses) and output sources (e.g., output buses, networks) is modeled in a verification layer that employs multiple queues to simulate receipt of input data, submission to an output port and transmission from the device. Call backs are employed to signal completion of events related to receipt of data at the device and modeling of data processing within the verification layer. As call backs are resolved, corresponding tasks are executed to advance the processing of the data through the verification layer. A device-specific algorithm is executed in the verification layer to predict the ordering of output from the device, and that output is compared to the predicted output by a transmission checker.

Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

Abstract: A scheme for profiling function calls for an application is provided. The scheme includes tracking invocations of the application methods and executing a sampling thread concurrently with the application. The executing includes periodically activating the sampling thread to set a flag to a true state and checking if the flag is true for the tracked invocations for the application methods. If the flag is true, then the scheme includes recording a current timestamp for the application method and charging a time difference between the current timestamp and a previous timestamp to the application method. A computer readable media and a system for performing profiling for an application are also provided.

Abstract: One embodiment of the present invention provides a system that optimizes subset selection to facilitate parallel training of a support vector machine (SVM). During operation, the system receives a dataset comprised of data points. Next, the system evaluates the data points to produce a class separability measure, and uses the class separability measure to partition the data points in the dataset into N batches. The system then performs SVM training computations on the N batches in parallel to produce support vectors for each of the N batches. Finally, the system performs a final SVM training computation using an agglomeration of support vectors computed for each of the N batches to obtain a substantially optimal solution to the SVM training problem for the entire dataset.

Abstract: A method for updating agent configuration data that includes specifying an arbitrary configuration Uniform Resource Locator (URL) for an agent, wherein the arbitrary configuration URL is not associated with a physical web resource, intercepting a modify request to the arbitrary configuration URL by the agent, updating agent configuration data in response to the modify request, and updating an agent module using updated agent configuration data.

Abstract: In some embodiments, a method is provided for determining a localized region of overlap of first and second features from respective first and second conductive layers, and determining which enclosure rules to apply to vias formed between the first and second features. In a further aspect of the invention, a method may be provided to determine whether to apply symmetric or asymmetric via metal enclosure rules to a feature as a function of the local environment of the feature. In another aspect of the invention, a computer program product is provided to encode instructions for performing such a process.

Abstract: In a garbage collector that employs the train algorithm, some objects in the collection set are evacuated from the collection set, even though they are referred to only by weak references, in order to keep the data that they contain available for post-mortem processing. The destinations to which at least some such objects are evacuated are chosen independently of where the weak references to them are located.

Abstract: A heat sink uses a pump assembly to generate a radial magnetic field. Pipes arranged to house a portion of a first channel and a portion of a second channel are formed in the heat sink. The direction of fluid flow in the first channel and the direction of fluid flow in the second channel is dependent on the radial magnetic field. The radial magnetic field causes fluid in the first channel to flow toward a heat source and fluid in the second channel to flow away from the heat source, thereby resulting in heat transfer between the first and second channels and between the heat sink and the respective first and second channels. The heat sink may also use a heat exchanger assembly that is connected to the heat source, where the heat exchanger assembly is formed of a plurality of channels that each propagate fluid in one of the directions of the first channel and the second channel.

Abstract: A technique for providing service processor (SP) access to registers, e.g., control and status registers (CSRs), located within hardware modules of a computer system, ensures access to the CSRs within a predetermine time period. The computer system includes a host module (HM) and a plurality of client modules (CMs). The CMs each include one or more associated registers, and each of the CMs is separately addressable. At least one of the CMs operates at a different clock frequency than the remaining CMs and includes a clock synchronizer, which provides a clock signal to facilitate reading of or writing to the associated registers of the CM by the HM.

Abstract: In one embodiment, a method and apparatus for ring optimization for data sieving writes is disclosed. The method includes dividing a file range to be written to via a data sieving write operation into N groups, where N is greater than or equal to a number of processes writing to the memory, determining an offset assigned to each process, the offset being a distance from a beginning of the file range at which each process starts its writing, simultaneously writing by each process to the group of the file range determined by the associated offset of each process, and moving, by each process, to the next available subsequent group when a process completes the writing. Other embodiments are also disclosed.

Abstract: A method for inserting repeaters in an integrated circuit includes establishing a set of initial constraints for a given set of buses; assigning at least one repeater corresponding to each of the given set of buses based on the set of initial constraints; progressively relaxing the set of initial constraints to form a new set of constraints for a new set of buses and assigning at least one repeater corresponding to each of the new set of buses based on the new set of constraints; and routing assigned repeaters to each of the new set of buses in the integrated circuit.

Abstract: One embodiment of the present invention provides a system that enforces memory-reference ordering requirements at an L2 cache. During operation, the system receives a load at the L2 cache, wherein the load previously caused a miss at an L1cache. Upon receiving the load, the system performs a lookup for the load in reflections of store buffers associated with other L1 caches. These reflections are located at the L2 cache, and each reflection contains addresses for stores in a corresponding store buffer associated with an L1 cache, and possibly contains data that was overwritten by the stores. If the lookup generates a hit, which indicates that the load may potentially interfere with a store, the system causes the load to wait to execute until the store commits.

Abstract: An apparatus and method for efficiently managing store buffer operations is described in connection with a multithreaded multiprocessor chip. A CMT processor keeps track of stores by maintaining two store counters in the instruction fetch unit (IFU). A speculative store counter in the IFU tracks stores in flight to the store buffer as well as stores already in the store buffer. A committed store counter in the IFU tracks the number of stores actually in the store buffer. The store buffer provides allocate and deallocate signals to accurately maintain the committed store counter. The IFU stops issuing stores to the store buffer once the speculative counter has reached a threshold value. Upon a flush, the IFU sets the speculative counter equal to the committed store counter. In this way, an efficient feedback mechanism is provided for preventing store buffer overflow that minimizes the store buffer size, operations time and power usage.