Abstract: One embodiment of the present invention provides a system that facilitates biased locking of objects within an object-based computing system. The system encounters a lock-acquisition operation while executing a current thread, wherein the lock-acquisition operation attempts to acquire a lock for an object. In response to the lock-acquisition operation, the system examines synchronization information associated with the object, wherein the process of examining the synchronization information does not involve atomic operations. If the synchronization information indicates that the lock is biasable and that the lock is biased toward the current thread, the system allows the current thread to acquire the lock without updating the synchronization information.

Abstract: A system and method for application deployment in a server cluster from a central domain. The method may include assembling a set of source code and related resource files on an administration server coupled to an application repository. The method may also include compiling the set of source code and related resource files into an application and storing the application in the application repository. The application may then be deployed onto a first subset of servers in a cluster of servers and executed on the subset of servers. In one embodiment, the method may further include storing a different version of the application in the application repository and deploying the different version of the application onto a second subset of servers separate from the first subset of servers. The different version of the application may then be executed on the second subset of servers.

Abstract: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.

Abstract: A split hardware transaction may split an atomic block of code to be executed using multiple hardware transactions, while logically taking effect as a single atomic transaction. A split hardware transaction may use software to combine the multiple hardware transactions into one logically atomic operation. In some embodiments, a split hardware transaction may allow execution of atomic blocks including non-hardware-transactionable (NHT) operations without resorting to exclusively software transactions. A split hardware transaction may maintain a thread-local buffer logs all memory accesses performed by the split hardware transaction. A split hardware transaction may use a hardware transaction to copy values read from shared memory locations into a local memory buffer.

Abstract: An indirect cooling liquid embedded package design for use with a computer central processor unit is suitable for thermal management of high heat dissipation electronic components such as server processors. The indirect contact cooling liquid embedded packaged CPU has mechanical coupling and embedded plumbing that attaches to the board pumped liquid supply and indirect cooling of the heat-generating portion of the CPU with an embedded microchannel heat exchanger. The coolant package system for the CPU removes higher levels of heat indirectly from the core of the processors by convective cooling. Cooling liquid is introduced into the package of the server CPU by mechanically attaching the CPU to the board through a socket interconnect. Pins of the socket serves to provide electrical connection between the board and the CPU, while a few pins are designed for the purpose of inletting and outletting cooling liquid into and out of the CPU package.

Abstract: Mechanisms and techniques provide a system for tracking and reporting on the resolution of problems across multiple product areas. The system can receive a first problem definition and can define a first work item identifying a respective first resolution associated with the first problem definition. The system can further define a second work item identifying a respective second resolution associated with the first problem definition. Work items can be automatically generated by the system or users may manually create the work items. The system can also receive at least one work item update for at least one of the first and second work item. The work item update alters a resolution state associated with either the first and second work items for which the work item update is received. The system can also provide a problem resolution report for the first problem definition based upon a correlation of resolution states associated with at least the first and second work items.

Abstract: A system configured to detect faults in signal lines. A system includes a first component configured to communicate with a second component via a signal path including one or more signal traces. Sense signal lines are manufactured such that at some point they are in close proximity to a signal trace which is to be monitored. The sense signal lines are configured to use parasitic coupling to redirect a portion of a signal conveyed via a signal trace to a monitoring component. The first component is configured to convey a test signal indicative of a type of test via the signal path, and a reference signal to the monitoring component. The monitoring component is configured to utilize the reference signal to ascertain a presence or absence, or characteristics of a received redirected signal. The monitoring component may optionally utilize a locally generated reference signal.

Abstract: One embodiment of the invention provides apparatus including a data structure representing a fault tree for a system. The data structure comprises a plurality of events linked by propagations. Each event is classified as one of at least three possible event types. A first type of event is a problem event, which represents an underlying cause of misbehavior in the system. A second type of event is an error event, which represents an error in the system comprising an incorrect signal or datum. A third type of event is a report event, representing the formal detection by the system of an error. Each propagation in the fault tree denotes a cause and effect linkage from one event to another event. There are no propagations within the fault tree to a problem event.

Abstract: A memory is disclosed having one or more logic level reinforcement circuits (LLRC's) coupled to each wordline. Each LLRC has an input and an output, both of which are coupled to a corresponding wordline. The LLRC senses a present logic level on the wordline. If the present logic level is a first logic level, then the LLRC outputs a first logic level reinforcement signal onto the wordline to push the voltage on the wordline towards a desired voltage for that logic level. If the present logic level is the second logic level, then the LLRC outputs a second logic level reinforcement signal onto the wordline to push the voltage on the wordline towards a desired voltage for that logic level. By doing so, the LLRC compensates for the undesirable effects of gate leakage, and enables the memory to operate effectively and efficiently despite the gate leakage.

Abstract: A system for processing a packet, including a network interface card (NIC), including a plurality of hardware receive rings, a classifier configured to classify the packet and send the packet to one of the plurality of hardware receive rings, and a host, operatively connected to the NIC, including a virtual network stack including a virtual serialization queue, a virtual network interface card (VNIC) associated with the virtual serialization queue, a device driver associated with the VNIC and configured to store a function pointer and a token associated with one of the plurality of hardware receive rings, where the VNIC is configured to perform at least one selected from a group consisting of enabling bypass mode and disabling bypass mode by changing the function pointer stored in the device driver, where the function pointer is used to send the packet to the virtual serialization queue if the bypass mode is enabled.

Abstract: One embodiment of the present invention provides an integrated chip module and a corresponding method of manufacture that facilitates proximity communication. This module includes a base chip and a bridge chip, both of which include an active face, upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip, and the back face of the bridge chip is thinned via planarization or polishing.

Abstract: Mechanisms and techniques provide for authenticating devices in a network such as a Radio Frequency Identification (RFID) Network between control stations and one or more transceivers. A transceiver receives transceiver configuration information including a network address and transceiver authentication credentials and receives an authentication request from the control station. The transceiver applies authentication processing to request information within the authentication request in conjunction with the transceiver authentication credentials to produce an authentication response and transmits the authentication response to the control station to allow the control station to determine if the transceiver is authorized to communicate within the remote identification system.

Abstract: A mechanism is disclosed for enabling a plurality of nodes on a network to collaboratively share a file. In one implementation, each node maintains its own copy of the file, and each node may make updates to its copy of the file. Whenever a node does update the contents of a region of the file, that node sends out an update message. The update message comprises the updated content for the region that has been updated. The update message is forwarded to each of the other nodes. When each of the other nodes receives the update message, it updates its copy of the file with the updated content for the region. In this manner, the file is kept in sync on each of the nodes, and the user on each node is able to see changes made by users on the other nodes. Collaboration among the users is thus achieved.

Abstract: A method for checkpointing a system that includes receiving a stop command by an executing thread from a master, wherein the executing thread executes an operating system, continuing execution of the executing thread until a checkpoint is reached after receiving the stop command, halting execution of the executing thread at the checkpoint, and checkpointing the system by storing a state and a snapshot of memory.

Abstract: Split hardware transaction techniques may support execution of serial and parallel nesting of code within an atomic block to an arbitrary nesting depth. An atomic block including child code sequences nested within a parent code sequence may be executed using separate hardware transactions for each child, but the execution of the parent code sequence, the child code sequences, and other code within the atomic block may appear to have been executed as a single transaction. If a child transaction fails, it may be retried without retrying the parent code sequence or other child code sequences. Before a child transaction is executed, a determination of memory consistency may be made. If a memory inconsistency is detected, the child transaction may be retried or control may be returned to its parent. Memory inconsistencies between parallel child transactions may be resolved by serializing their execution before retrying at least one of them.

Abstract: An apparatus includes a server comprising n operating system images and an IOV aware root complex; a plurality of physical I/O devices comprising n virtual I/O functions; and a PCI Express bus operatively connected to the server and the plurality physical I/O devices via the root complex, wherein the root complex is operable to provide communication between the n operating system images and the n virtual I/O function, and wherein the server and the plurality of physical I/O devices are modules in a chassis.

Abstract: An electromagnetic interference shield for a hard disk drive has a metal shield portion, a plurality of top fingers, bottom fingers, left fingers, and right fingers disposed on four sides of the metal shield portion, and bars tying the tips of the plurality of top fingers together, the tips of the plurality of bottom fingers together, the tips of the plurality of right fingers together, and the tips of the plurality of left fingers together. Each of the plurality of top fingers and bottom fingers are wider than each of the plurality of left fingers and right fingers. Each of the plurality of top fingers, bottom fingers, left fingers, and right fingers has a perpendicular jog at a base portion thereof.

Abstract: A “sombrero” bridge transports signal communication between a processor and one or more cache memories. The bridge surrounds the processor's perimeter, and includes an aperture opposite the processor through which power and data can be provided to the processor from another device. The bridge exchanges signals with the cache memories via capacitively coupled proximity connections. The bridge communicates with the processor via conductive (e.g. wire) connections and optionally proximity connections. Spacing between opposing pads of the proximity connection(s) between the bridge and the cache memories can be provided by recesses in a surface of the cache memory, corresponding recesses in an opposing surface of the bridge, and a ball for each matching pair of corresponding cache memory and bridge recesses. The ball fits in and between the recesses of the matching pair. The recess depths and ball diameter(s) constrain a minimum distance between opposing pads of the proximity connection(s).

Abstract: A method for memory management that includes receiving a request for memory space, identifying a first memory module from a plurality of memory modules based on a first memory power management policy, wherein the first memory power management policy specifies how to allocate memory space in the plurality of memory modules to satisfy a power consumption criteria, and allocating the memory space on the first memory module.

Abstract: An implicitly pulsed dual edge triggered pulsed latch. The implicitly pulsed latch includes an overlapping clock generator and a transparency circuit designed to cause a transparent latch circuit to become transparent on each edge of a clock signal. A logic value on the input node of the latch is transferred to the output node of the latch in response to each clock edge transition. An explicitly pulsed dual edge triggered pulsed latch including a pulse generator and a transparent latch circuit. The explicitly pulsed latch includes a symmetrical pulse generator designed to cause the latch circuit to pass a logic value from the input node of the latch to the output node of the latch in response to a pulse on the clock node.