Abstract: A multidata framework is provided to allow multiple payload buffers to be associated with a single multidata message. In the multidata framework of the present invention, a number of payload buffers are associated with the multidata following allocation of the multidata header buffer. The number of payload buffers can reside at disjoint virtual address locations in memory. Each payload buffer is assigned an index for identification purposes. A number of packets are defined to represent the multidata message. Each packet includes a header portion and a payload portion. The payload portion is defined as a set of payload spans. Each payload span is mapped to the payload portion of the appropriate packet by an appropriate payload buffer index and address range in the appropriate payload buffer. Thus, a packet's payload portion can include payload spans that are located at disjoint virtual address location in memory.

Abstract: A computer software tool for processing timecard related information representing services to be billed wherein the software tool is part of a purchase order procurement system. The software tool is single software system for procurement services composed of a timecard module integrated with a procurement management module. The timecard process includes a base of functions compatible with existing procurement software systems. The system allows a contractor (buyer) to generate a timecard including services, descriptions and amounts. The generation of the timecard triggers a notification to an approving body which then either approves or declines the timecard. Once approved, timecard information can be exported, e.g., using XML, to a payroll or other external service.

Abstract: A memory system comprising memory modules including memory chips including integrated switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a switching circuit within a memory chip detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data.

Abstract: One embodiment of the present invention provides a system that supports inserting or deleting nodes at any location within a doubly-linked list which is lock-free, wherein lock-free means that the doubly-linked list can be simultaneously accessed by multiple processes without requiring the processes to perform locking operations (non-blocking) and furthermore that a finite number of steps performed by a process will guarantee progress by at least one process (lock-free). During operation, the system receives a reference to a target node to be deleted from the doubly-linked list. Next, the system atomically marks a forward pointer in the target node to indicate that the target node is deleted, wherein the forward pointer contains the address of an immediately following node in the doubly-linked list, and wherein the marking operation does not destroy the address of the immediately following node. Additional cleanup steps are then done by this or any other process.

Abstract: During two-pass sliding compaction, a heap may first be logically divided into fixed-sized segments, or chunks, and information regarding each chunk, known as per-chunk metadata, may be saved for use during the second, sliding phase. In addition to the per-chunk information, information regarding the location and size, called object extent information, may also be saved during the marking phase of two-pass sliding compaction. In the sliding phase of two-pass sliding compaction, live objects are moved to their respective destinations in the heap after first updating any object references in the objects. The order of objects being moved may be maintained across heap compaction. By relying upon the per-chunk and object extent information saved during the marking phase, objects may be processed individually and independent of each other during the sliding phase, according to some embodiments.

Abstract: Embodiments of the present invention provide a system that maintains load-marks on cache lines. The system includes: (1) a cache which accommodates a set of cache lines, wherein each cache line includes metadata for load-marking the cache line, and (2) a local cache controller for the cache. Upon determining that a remote cache controller has made a request for a cache line that would cause the local cache controller to invalidate a copy of the cache line in the cache, the local cache controller determines if there is a load-mark in the metadata for the copy of the cache line. If not, the local cache controller invalidates the copy of the cache line. Otherwise, the local cache controller signals a denial of the invalidation of the cache line and retains the copy of the cache line and the load-mark in the metadata for the copy of the cache line.

Abstract: A method for controlling a software lock acquirable by processors in a plurality of nodes of a multiprocessing system is disclosed. The method comprises a first processor of a first node of the plurality of nodes acquiring the lock, and the first processor selectively releasing the lock in a first state that allows other processors within the first node to acquire the lock but that prevents processors in a remote node of the plurality of nodes from obtaining the lock. In another embodiment, a method comprises a first processor of a first node attempting to acquire the lock, the first processor determining whether another processor within the same node is remotely spinning on the lock, and the first processor remotely spinning on the lock in response to determining that another processor in the same node is not remotely spinning on the software lock.

Abstract: One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. Upon encountering a non-data dependent stall condition, the system performs a checkpoint and commences execution of instructions in scout mode, wherein instructions are speculatively executed to prefetch future memory operations, but wherein results are not committed to the architectural state of a processor. When the system executes a load instruction during scout mode, if the load instruction causes a lower-level cache miss, the system allows the load instruction to access a higher-level cache. Next, the system places the load instruction and subsequent dependent instructions into a deferred queue, and resumes execution of the program in scout mode.

Abstract: In general, in one aspect, the invention relates to a method for integrating dimensional analysis in a program comprising defining a specific dimension class within the program, wherein the specific dimension class is an instance of the dimension meta-class, defining an instantiation of a unit class within the program, wherein the instantiation of the unit class comprises the specific dimension class as a type parameter associated with the instantiation of the unit class, defining a method within the program using the instantiation of the unit class and the specific dimension class, and compiling the program to generate an executable code corresponding to the program, wherein the program is written in an object-oriented language.

Abstract: In one embodiment, a node comprises at least one memory control unit configured to couple to an industry standard memory interface for coupling to a memory; and at least one coherence unit configured to transmit and receive coherence messages to and from other nodes to maintain coherent memory among the nodes. The coherence messages are conveyed on a second interface to which the coherence unit is coupled, wherein the second interface includes at least a physical layer as specified by the industry standard memory interface.

Abstract: An apparatus comprises an encode circuit coupled to receive input data and configured to generate corresponding codewords and a decode circuit coupled to receive codewords and detect an error in the codewords (and may, in some cases, correct the error). Each codeword comprises a plurality of b-bit portions (b is an integer greater than one). Additionally, each codeword comprises a first set of b check bits used to detect a magnitude of an error in a b-bit portion of the plurality of b-bit portions. Each codeword further comprises a second set of w check bits used to locate which one of the plurality of b-bit portions is the b-bit portion containing the error (w is an integer greater than zero and less than b).

Abstract: A method for communication includes coupling a client device to communicate with a host computer over a serial link. Responsively to a call from a client application running on the client device, the client device submits a request over the serial link to the host computer to open a proxy connection for communication between the client application and a server application. Responsively to the request, the host computer creates a socket for communication with the server application, so as to establish the proxy connection via the socket. The host computer and client device convey data between the server application and the client application over the serial link using the proxy connection.

Abstract: A system may include multiple nodes, and each node may include a processing subsystem and an interface that are coupled by an address network and a data network. The nodes' interfaces may communicate over an inter-node network. Each processing subsystem may transition an access right to a coherency unit in response to a data packet on the data network and transition an ownership responsibility for the coherency unit in response to an address packet on the address network such that the access right transitions at a different time than the ownership responsibility transitions. An interface within a node may be configured to delay providing a data packet on the node's data network until the interface receives an indication that shared copies of the coherency unit in other nodes have been invalidated.

Abstract: A reorder mechanism for use with a relaxed order interconnect device. The reorder mechanism includes a buffer module and a reorder module coupled to the buffer module is disclosed. The reorder module enables movement of multiple packets between a plurality of resources. The movement of multiple packets of information has a relaxed ordering of data transfers associated with multiple packets and also a relaxed ordering of data transfers associated with any single packet.

Abstract: A distributed simulation system may include a plurality of nodes arranged to perform a simulation of a system under test. The plurality of nodes are configured to communicate simulation commands and signal values for the system under test using message packets transmitted between the plurality of nodes. At least one of the plurality of nodes is configured to log the message packets in one or more log files during the simulation.

Abstract: A method for tracing an instrumented program on a processor having an x86 architecture, including triggering a probe in the instrumented program, obtaining an original instruction associated with the probe, loading the original instruction into a scratch space, loading a jump instruction for the x86 architecture into the scratch space wherein the jump instruction includes a next program counter value, executing the original instruction in the scratch space using a thread, and executing the jump instruction in the scratch space using the thread.

Abstract: A computer system comprises a plurality of processing modules, each operable to provide a service to an external entity. Each processing module has a processor and a memory. A storage module is provided, operable to store information required by the processing modules to provide the service. A switching module is also provided, operable to provide a switching service between the processing module and storage module and between the processing module and an external entity.

Abstract: Embodiments of the present invention provide a system that handles load-marked and store-marked cache lines. Upon asserting a load-mark or a store-mark for a cache line during a given phase of operation, the system adds an entry to a private buffer and in doing so uses an address of the cache line as a key for the entry in the private buffer. The system also updates the entry in the private buffer with information about the load-mark or store-mark and uses pointers for the entry and for the last entry added to the private buffer to add the entry to a sequence of private buffer entries placed during the phase of operation. The system then uses the entries in the private buffer to remove the load-marks and store-marks from cache lines when the phase of operation is completed.

Abstract: Disclosed herein is a method for scheduling computing jobs for a compute farm. The method includes: receiving a plurality of computing jobs at a scheduler; assigning a signature to each computing job based on at least one computing resource requirement of the computing job; storing each computing job in a signature classification corresponding to the signature of the computing job; and scheduling at least one of the plurality of computing jobs for processing in the compute farm as a function of the signature classification.

Abstract: A method for use in a computer system provides a dynamic, “self tuning” soft-error-rate-discrimination (SERD) method and apparatus. Specially designed SRAMs or other circuits are “tuned” in a manner that gives them extreme susceptibility to cosmic neutron events (soft errors), higher than that of the “regular” SRAM components, memory modules or other components in the computer system. One such specially designed SRAM is deployed per server. An interface algorithm continuously sends read/write traffic to the special SRAM to infer the soft error rate (SER), which is directly proportional to cosmic neutron flux. The inferred cosmic neutron flux rate is employed in a Poisson SPRT algorithmic approach that dynamically compensates the soft error discrimination sensitivity in accordance with the instantaneous neutron flux for all of the regular SRAM components in the server.