Abstract: Transparent routing within the cluster is achieved (without changing the networking code on each node of the cluster) by using a pair of modules interposed appropriately on the networking stack. In a "clustered" system built out of several computers, using the present invention, the networking subsystem appears to applications as if the applications are running on a single computer. In addition, no modifications to the networking code is needed. The present invention is extensible to a variety of networking protocols, not just TCP/IP as the packet filter allows the routing within the cluster to be done dynamically. No modifications to the applications is needed (same binaries will work). A packet filter and remote communication between the modules through IDL enable the modules to do their job. A name server that maintains the port name space is used.
Type:
Grant
Filed:
November 22, 1995
Date of Patent:
September 8, 1998
Assignee:
Sun Microsystems, Inc.
Inventors:
Jose M. Bernabeu-Auban, Yousef A. Khalidi, Vladimir Matena, Kenneth W. Shirriff
Abstract: A frame buffer including a memory array, circuitry for accessing the array, a plurality of latches each capable of storing a plurality of pixel values equivalent to a large portion of a row of pixels in the array which may be read simultaneously from the array, and circuitry for writing simultaneously to the memory cells of a row of the array the data stored in the latches whereby a row of pixels may be read and written back to the array bus in a minimum time period.
Type:
Grant
Filed:
November 22, 1996
Date of Patent:
September 8, 1998
Assignees:
Samsung Semiconductor, Inc., Sun Microsystems, Inc.
Inventors:
Curtis Priem, Chris Malachowsky, Rick Silverman, Shuen Chin Chang
Abstract: A method for selecting a set of test cases which may be used to test a software program product is disclosed. The program to be tested may have a number of code blocks that may be exercised during execution of the program. The method includes identifying each of the code blocks that may be exercised, and determining a time for executing each of the test cases in the set. A set of the test cases is then selected that exercises a maximum number of the identified code blocks that can be exercised in a minimum time. The selection step may be performed by executing a genetic algorithm for determining which subset of test cases to use, using a combination of time and coverage as a fitness value.
Abstract: The present invention teaches a variety of methods, data structures and apparatus for use in representing and traversing hierarchical netlists. According to a first embodiment of the present invention, a hierarchical netlist which represents an electronic device is stored in a computer readable medium and includes a module data structure and a hierarchical data structure. The module data structure includes a first module and a list identifying each instance of the first module present in the hierarchical netlist. The hierarchical point data structure represents a first hierarchical element in the hierarchical netlist and is arranged to identify a selected device element represented in the first module. Additionally, the hierarchical point data structure is capable of identifying a plurality of unique occurrences of separate but identical device elements that are represented by the first hierarchical element.
Abstract: Improved circuits for implementing various embodiments of high performance arbiters are disclosed. In one embodiment, a late-done arbiter is implemented by combining a late-decision arbiter with a decision storage (or queue) device. In another embodiment, an arbiter implementation that extends the amount of storage available for decisions is disclosed. A decision making device such as a simple arbiter is followed by a decision storage device such as a queue or a first in first out (FIFO) register of any number of stages. The decision storage device following the arbiter allows the arbiter to report each decision as quickly as it can and to start the next decision making cycle.
Abstract: The preferred embodiment of the present invention provides a method and system for resizing subtitles of a video without resizing the video image itself. The preferred embodiment is typically user initiated. First, a user requests a video from a server. The server transmits two data streams, a video/audio (hereinafter referred to as "video") data stream and a text data stream, over the network to the client computer. The client receives and sends both data streams to a viewer program (e.g., a browser). The browser combines the two data streams into a single window as seen by the user.Since the video and subtitles are sent as two separate streams of information, upon user request the browser is able to resize the subtitles and the subtitle viewing area independently from resizing the video image. The browser resizes the subtitles by rendering the subtitles in a user selected font size.
Abstract: A method and apparatus for providing versioning information for a plurality of software objects. When an object is compiled and linked, at build time, the link-editor creates a version definition section and a version symbol section in the object that specify the global symbols defined in various versions of the object. The object can be a shared object, a relocatable object, or a dynamic executable object. When an application software program is linked with the versioned object, at build time, the linker-editor creates a version dependency section in the resulting dynamic executable object that specifies which version of the object is required for execution of the software application program. At runtime, the runtime-linker determines whether all required versions of the object are present before the program is executed. The invention allows the definition of "weak" versions that do not contain new global symbols.
Abstract: A debugger for use in connection with a parallel computer including a plurality of processing nodes. The debugger enables the operator to establish a processing node set in response to certain criteria, such as the respective identifications of the processing node and their prior processing under the debugger. The debugger, in response to a processing node set establishment command from the operator, enables each processing node to establish and condition a set membership flag in response to the operator-supplied set membership criteria. The debugger is then responsive to a debugging command from the operator to enable the processing nodes to use their respective set membership flags to condition their execution of the debugging command.
Type:
Grant
Filed:
May 15, 1995
Date of Patent:
September 8, 1998
Assignee:
Sun Microsystems, Inc.
Inventors:
Joshua E. Simons, Karen C. Jourdenais, Steven J. Sistare
Abstract: A non-volatile caching system and a method for implement such a system is disclosed. The system is particularly applicable to rotating magnetic media such as hard disk drives. The system retains data even in the event of system shut-down and re-boot. The system is capable of rapidly caching data from large, randomly accessed files, such as databases, in a space-efficient manner. The cached data can be stored in nearly any standard or non-standard format on the magnetic media. A conversion routine converts CD-ROM file names or network file names to local hard disk drive file names and back. A mini-database is created for each cached file on the hard disk drive. The mini-data base maps randomly-accessed blocks of data within the cached file on the local hard disk drive.
Abstract: A communication subsystem for a digital computer system, which processes application programs under a base operating system (such as the MS-DOS operating system) in a first processor operational mode (such as the V86 mode), and also under an enhanced operating system (such as Microsoft Windows) during a session under a second processor operational mode (such as a privileged or user mode). During an enhanced operating system session, the enhanced operating system makes use of at least some selected elements of the base operating system, in particular relation to the current invention some of the communications drivers. The communication subsystem enables the digital computer system to transfer messages, each comprising a series of characters, over a communications network.
Abstract: A metadisk driver functionally intermediate a computer operating system and one or more metadrivers and underlying layered drivers provides a driver rename/exchange function which does not depend on any particular driver having knowledge of the private data structures of any of the other drivers. The rename/exchange technique implemented thereby may be conducted while the underlying devices are on-line and comprise atomic operations which are, therefore, recoverable inasmuch as the operation will have either been completed or will not be committed in the event of any interruption.
Type:
Grant
Filed:
April 15, 1996
Date of Patent:
September 1, 1998
Assignee:
Sun Microsystems, Inc.
Inventors:
Steven T. Senator, Dale R. Passmore, Robert S. Gittins
Abstract: In a processor, a method for performing table-lookup transformation through a look-up table a source image having a plurality of source pixels to derive a destination image having a plurality of destination pixels. The method includes the step of deriving, for each value in a source pixel of the plurality of source pixels, a look-up result. The aforementioned look-up result represents a value in a corresponding destination pixel of the plurality of destination pixels. The method further includes the steps of loading a plurality of the look-up results into a plurality of graphics registers in the processor and accumulating the plurality of the look-up results in the plurality of graphics registers into an accumulation register in the processor. Additionally, there is also provided the step of storing the accumulation register into the destination image.
Type:
Grant
Filed:
November 27, 1995
Date of Patent:
September 1, 1998
Assignee:
Sun Microsystems, Inc.
Inventors:
Peter Farkas, Stephen K. Howell, Daniel S. Rice
Abstract: Memory space in the lower-level cache (LLC) of a computer system is allocated in cache-line sized units, while memory space in the higher-level cache (HLC) of the computer system is allocated in page sized units; with each page including two or more cache lines. Accordingly, during the execution of a program, cache-line-sized components of a page-sized block of data are incrementally stored in the cache lines of the LLCs. Subsequently, the system determines that it is time to review the allocation of cache resources, i.e., between the LLC and the HLC. The review trigger may be external to the processor, e.g., a timer interrupting the processor on a periodic basis. Alternatively, the review trigger may be from the LLC or the HLC, e.g., when the LLC is full, or when usage of the HLC drops below a certain percentage.
Abstract: A method and lexical analyzer for diagnosing lexical errors in a stream of symbols. An error-diagnosing lexical analyzer is constructed by a lexical analyzer generator based on a list of regular expression patterns. The list of regular expression patterns includes patterns which define specific invalid lexeme types as well as specific valid lexeme types. The lexical analyzer generated based on the list of regular expression patterns has a first plurality of states and a second plurality of states. Each state of the first plurality of states represents a specific valid lexeme type and is associated with a label identifying the specific valid lexeme type. Each state of the second plurality of states represents a specific invalid lexeme type and is associated with a label identifying the specific invalid lexeme type. The lexical analyzer reads symbols from a stream of symbols and changes state based on the symbols according to transition rules.
Abstract: A cache only client-server configuration which provides the performance benefits of "dataless" client operation with the administrative efficiencies of a "diskless" client-server configuration. Utilizing cache only clients, the performance of stand-alone systems can be approximated utilizing a relatively small disk drive as a local data cache. The cache only clients may be considered as interchangeable units in that they hold no critical data and any data held on the local disk is a "clone" of the master copy held on the server. System configuration, administration and maintenance costs are dramatically reduced since software installation, distribution and backup may be managed at the server.
Abstract: A Method for increasing data-processing speed in computer systems containing at least one microprocessor (1), a memory device (3), and a cache (2,4) connected to the processor, in which the cache (2,4) is arranged to fetch data from the addresses in the memory device (3) requested by the processor (1) and then also fetches data from one or several addresses in the memory device (3) not requested by the processor (1). The computer system includes a circuit called the stream-detection circuit (5), connected to interact with a cache (2,4) such that the stream-detection circuit (5) detects the addresses which the processor (1) requests in the cache (2,4) and registers whether the addresses requested already existed in cache (2,4) . The stream-detection circuit (5) is arranged such that it is made to detect one or several sequential series of addresses requested by the processor (1) in the cache (2,4).
Abstract: A dual-ported tag array of a cache allows simultaneous access of the tag array by miss data of older LOAD instructions being returned during the same cycle that a new LOAD instruction is accessing the tag array to check for a cache hit. Because a load buffer queues LOAD instructions, the cache tags for older LOAD instructions which missed the cache return later when new LOAD instructions are accessing a tag array to check for cache hits. A method and apparatus for calculating and maintaining a hit bit in a load buffer perform the determination of whether or not a newly dispatched LOAD will hit the cache after it has been queued into the load buffer and waited for all older LOADs to be processed. A load buffer data entry includes the hit bit and all information necessary to process the LOAD instruction and calculate the hit bits for future LOAD instructions which must be buffered.
Type:
Grant
Filed:
October 7, 1997
Date of Patent:
September 1, 1998
Assignee:
Sun Microsystems, Inc.
Inventors:
Dale Greenley, Leslie Kohn, Ming Yeh, Greg Williams
Abstract: A method and apparatus for facilitating the streaming of data over a system bus between a memory and a DMA device. This is accomplished by doing a speculative cache look-up, or snoop, on a next cache line during or immediately following the access of a current cache line. This is done for DMA transfers when the first DMA address is received, and before subsequent addresses are received. Thus, a determination of whether the cache line is in the cache can be done in advance, allowing the next cache line of data to stream over the bus to or from the cache without waiting for the next address from the system bus or requiring a rearbitration for the system bus.
Abstract: A system for screening data packets transmitted between a network to be protected, such as a private network, and another network, such as a public network. The system includes a dedicated computer with multiple (specifically, three) types of network ports: one connected to each of the private and public networks, and one connected to a proxy network that contains a predetermined number of the hosts and services, some of which may mirror a subset of those found on the private network. The proxy network is isolated from the private network, so it cannot be used as a jumping off point for intruders. Packets received at the screen (either into or out of a host in the private network) are filtered based upon their contents, state information and other criteria, including their source and destination, and actions are taken by the screen depending upon the determination of the filtering phase. The packets may be allowed through, with or without alteration of their data, IP (internet protocol) address, etc.
Type:
Grant
Filed:
May 18, 1995
Date of Patent:
September 1, 1998
Assignee:
Sun Microsystems, Inc.
Inventors:
Geoffrey G. Baehr, William Danielson, Thomas L. Lyon, Geoffrey Mulligan, Martin Patterson, Glenn C. Scott, Carolyn Turbyfill
Abstract: A simplified or pseudo least-recently-used (LRU) process and circuit in a cache memory or translation lookaside table (TLB) maintains status bits to identify which entries are valid and which entries have been recently used. If none of the entries are invalid, only entries not indicated as recently used are replaced (or overwritten). When all entries are indicated as valid and recently used, status bits other than the status bits for the entry last accessed are changed to indicate that the corresponding entries have not been recently used. Accordingly, those entries can be replaced, but the most recently used entry still cannot be replaced. This makes the pseudo LRU process closer to a full LRU process when compared to pseudo LRU processes which clear all status bits simultaneously. Complexity for the LRU process is not greatly increased because the address generated for the most recent access of an entry can be used to identify the bit which is not changed.