Abstract: A system for converting between parallel data and serial data is described. In the system 10, individual bits of the parallel data 12 are latched into individual registers 117. Each register 117 is coupled to a corresponding AND gate 110 which is also connected to receive phased clock signals. The output terminals of the AND gates 110 are connected to an OR gate 115. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Abstract: Image operations are implemented using a specially developed instruction set in a parallel processing environment that maximizes parallelization of operations. Graphics data partitioned addition and multiplication instructions allow for simultaneous addition or multiplication of multiple words of graphics data in parallel using a number of processing sub-units of a graphics execution unit.

Abstract: A Web document based GUI for use on a client computer that is networked with server computers. The GUI enables a user of the client computer to initiate specific operations that are performed on the client computer and that define a particular application. The GUI comprises GUI Web documents and a Web browser. Each GUI Web document is located at the client computer or one of the server computers and comprises one or more links and one or more applets. Each link provides a link to a corresponding GUI document when selected by the user with the client computer while being displayed on the client computer. Each respective applet generates, when executed on the client computer, an interactive image that is displayed on the client computer. The user can initiate a respective operation (i.e., one of the GUI's specific operations) by acting on the interactive image with the client computer to invoke the respective applet to perform the respective operation on the client computer.

Abstract: A networked computer system contains a number of host computers with servers that provide various functionality to distributed clients on the network. Clients are able to access runtime information about servers on remote host computers, even where the clients have only object references to the servers through the presence of an embedded first class object within each server process. The first class object can be used to determine the process identification of the server process, counts of active objects and implementations in the server process, and to control tracing and logging functions provided by application programming interfaces utilized by the server.

Abstract: Disclosed is a system for automatically generating tables of buffer data which can be used during integrated circuit design to select appropriate buffers for signal distribution networks. The generated buffer data may be used by automated place and route systems to generate signal distribution networks having minimal skew. In the table, incrementally varying network features or criteria are provided (in the form of a table or list for example). Examples of such features include the length of a line connecting an L4 buffer to one or more L5 buffers and the number of L5 buffers driven by a single L4 buffer. For each incremental value of the network feature or features, one or more buffer types is specified. These buffer types have been previously modeled in the environment of the incremental value of the network features and found to meet certain criteria necessary to minimize skew.

Abstract: A method and apparatus for event-tagging data entries as separate data segments in a data file. The data file is stored in the memory of a computer including a processor that executes instructions to carry out the method of the invention. As a user enters data, such as with a computer "pen" in a pen-driven notebook computer, the processor determines whether each data entry is one of a set of predefined data entry events. Such events may include areas on the screen that the user is entering his or her notes, such lines or paragraphs, such that whenever the user begins a new line or paragraph, that is tagged as a new event. An event may also be a particular time interval; for instance, data entry may be tagged every minute, or every ten minutes. An event may also relate to the type of data that the user is entering, such as graphical data vis-a-vis handwritten or text data, and/or may relate to the fact that a given data entry is of a different type of data than an adjacent data entry.

Abstract: A fault tolerant computer system includes a number of lockstep subsystems, each of which comprises a parallel input signature generator, used for data compression to allow practical comparison of the operation of internal modules of the lockstep subsystem, and a logic analyzer which stores the outputs of the internal modules of the lockstep subsystem. A signature comparator is connected to receive the signatures from the signature generators of the individual lockstep subsystems. The signature comparator generates a trigger signal for triggering the logic analyzers on detecting a difference in the signatures. The logic analyzers store enough states to include the first difference from a module following a detected difference in the signature outputs. The logic analyzer traces are searched automatically after an out-of-sync event to locate the first difference in operation and to determine which internal module provided the faulty output and then that module is labelled as broken.

Abstract: A pixel of a color video image is converted from one color format having luminance and chrominance signals, e.g., YUV format, to a destination format, e.g., RGB or CMY formats, by forming luminance and chrominance component words which include partitioned words representing various color components of the luminance and chrominance signals. The luminance and chrominance component words are summed using a partitioned addition operation to thereby accumulate the various color components of the luminance and chrominance signals simultaneously and in parallel. Formation of the luminance and chrominance component words is, in some instances, done by a load and store unit of a central processing unit while a graphics execution unit simultaneously sums the luminance and chrominance components using the partitioned addition operation. By using this technique, conversion of pixels of a color motion image from YUV format to a different format, e.g.

Abstract: A simplified comparison of register designations by using a window delta which indicates how much the window of an instruction differs from the current window register designation. Where registers are shared, the windows will either be the same or differ by one. Thus, a single bit can be used to indicate the window delta, and in combination with the logical register address, can be used to quickly determine whether there is a register match between instructions.

Abstract: An information transfer system transfers information, in the form of at least one digital data word, from an source operating in a first clock signal domain defined by a first clock signal, to a destination operating in a second clock signal domain defined by a second clock signal. The information transfer system includes a buffer, a buffer storage element, a buffer retrieval element and a synchronizer. The buffer storage element stores the data word in the buffer under control of a data word present indication, and the buffer retrieval element retrieves the data word from the buffer under control of the second clock signal and a synchronized data word present indication. The synchronizer generates the synchronized data word present indication in response to the first clock signal, the second clock signal, and the data word present indication, thereby to synchronize the data word present indication from the first clock signal domain into the second clock signal domain.

Abstract: The present invention pertains to a method and system for generating a sinusoidal signal as a combination of independently generated sinusoidal signals. A sinusoidal signal consisting of M data points per cycle is generated as a combination of P independently generated sinusoidal signals each consisting of M/P data points per cycle. Each independently generated sinusoidal signal is offset by P-1 data points and interleaved according to a prescribed sequence to represent the combined sinusoidal signal. The system of the present invention utilizes a processing unit having the capability of performing a single instruction on multiple data (SIMD) thereby executing multiple operations per cycle. This architecture enables each data point of the P independently generated sinusoidal signals to be generated simultaneously thereby decreasing the computational expense required to generate the sinusoidal signal.

Abstract: An improved prefetch program counter (PC) generation circuitry is provided to the prefetch and dispatch unit (PDU) of a pipelined computer system. The prefetch PC generation circuitry factors into consideration the states of dispatched CTIs in various pipeline stages, when generating a new prefetch PC value for instruction prefetching. The dispatched CTI state dependent prefetch PC generation circuitry includes storage circuitry, fetch control circuitry, and fetch PC generation circuitry. Together, the storage circuitry, the fetch control circuitry, and the fetch PC generation circuitry cooperate to prefetch instructions in a CTI state dependent manner, thereby improving the instruction prefetch rate. In one embodiment, two dynamically switchable instruction fetch queues are provided, with one being used as the sequential instruction fetch queue, and the other being used as the target instruction fetch queue.

Abstract: A test driver generator is provided for generating test drivers. The test driver generator receives test expressions designating execution sequences of test functions of software interfaces and corresponding attribute value specifications for the designated test functions' parameter attributes. Each test expression designating a number of test functions to be executed in a certain sequence, and each corresponding attribute value specification specifies selected attribute values of the test functions' parameter attributes. For each test expression and corresponding attribute value specifications of a software interface, the test driver generator, in response, generates a test driver that can execute the specified test functions in the designated order with all combinations of the selected attribute values of the test functions' parameter attributes.

Abstract: A clock recovery circuit employing a phase-locked loop design includes an N-to-1 multiplexer (MUX) coupled to a series of N latches which allows data to sampled at a frequency N times that of the clock. Incoming data is latched by each of the N latches, where each latch is clocked at a different phase of the clock signal such that the phase of the clock provided to the nth latch is shifted nT/N, where T is the period of the clock and n is an integer from 1 to N. The output terminals of the series of N latches are coupled to associated ones of input terminals of the N-to-1 MUX. The selection of MUX input terminals is controlled by the clock signal such that the incoming data signal is reconstructed at the output terminal of the MUX. In this manner, the incoming data signal is effectively sampled at N times the clock speed.

Abstract: A burn-in system for integrated circuits (ICs) generates thorough input stimuli from within the burn-in chamber. A very high node-toggle percentage within the IC being exercised is achieved, similar to that of a dynamic burn-in oven, even though the burn-in system of this invention has a cost and complexity similar to that of a static burn-in oven. This provides a cost-effective and reliable way to reduce the infant mortality of the ICs being exercised, or to estimate the longevity of the batch of ICs from which they came. The input-stimuli generator is based on a special-purpose burn-in controller IC. To better withstand the environmental stress within the burn-in chamber, the burn-in controller IC is fabricated using a robust IC technology, is operated at its nominal supply voltage and includes continuous fault tolerance features (such as self-test and/or voting). It is fully programmable to allow the same burn-in controller to be used with a variety of types of ICs being exercised.

Abstract: A computer system comprises a plurality of programs, each operating in an operating area such as a virtual machine. The programs are provided with a common data buffer for buffering data for processing by said programs. Each program also has a buffer control including at least one pointer for pointing to a buffer containing data to be processed by the program. One of the programs will initially process the data in the common data buffer and, after it is finished processing, will control the other program's buffer pointer to enable the other program to process the data in the common data buffer. By using the same buffer to contain data to be processed by both programs, the programs can avoid having to copy the data between private buffers maintained for each, which can assist in accelerating through-put by the computer system.

Abstract: A technique for system memory space address mapping in a multiprocessor computer system is provided. The disclosed mapping architecture may be applied to a multiprocessor computer system having multiple processing nodes (SMP nodes), where each processing node may include multiple processors. The system memory address space is split into different regions such that each of the n SMP nodes is assigned 1/n of the total address space. Cache coherency state information is stored for the memory in each SMP node. Memory regions may further be assigned to operate in one of three modes: normal, migratory, or replicate. When operating in normal mode, transaction to an address space assigned to a particular node are tried only locally in that node first. Transactions may be sent globally to other nodes if an improper cache coherency state is returned or if the address corresponds to a memory region assigned to another node. In migratory mode transactions are always sent globally.

Abstract: An electronic digital computer system includes a Graphical User Interface (GUI) for displaying graphical objects such as icon buttons, scrolling text lists, and text entry fields on a monitor. A keyboard includes a label key such as a conventional alternate (Alt) key which, when depressed, causes alphanumeric characters to be superimposed on the graphical objects. Depression of an alphanumeric key on the keyboard corresponding to the alphanumeric character superimposed on a selected object causes an associated operation to be launched. The GUI includes an object table having an entry for each graphical object. Each entry includes an object name, corresponding alphanumeric character, object type (e.g. icon button, text input field), and object display position. A display generator accesses the object table using the object names as inputs, obtains the alphanumeric characters as outputs, and superimposes and displays the alphanumeric characters on the objects.