Abstract: An apparatus and method for quickly and efficiently handling mispredicted branch instructions in a computer processor having multiple instruction execution pipelines and utilizing branch delay slot instructions. When a mispredicted branch occurs, all instructions that follow the branch in execution order, including the branch delay slot instruction, die in the pipeline. The delay slot, if it is to be executed, is then reissued to the pipeline.

Abstract: The present invention provides a user control mechanism for selectively retaining for display a document obtained from a network. The user control is located as an icon or symbol in the browser interface for ease of use. Subsequent documents which are downloaded from the network are displayed in a separate window of the display in the computing system, and these subsequent windows are also provided with the same user control mechanism. In particular, the user can selectively create a second browser display page by following a link contained in the first browser display page, without overwriting the contents of the first browser display page.

Abstract: Disclosed is an automated method for adjusting wire lengths between connected circuit elements of an integrated circuit. The method includes the following steps: (1) receiving a value specifying a wire length that must be provided between terminals of two integrated circuit elements in the integrated circuit design; (2) defining a routing region in which the wire can be routed; and (3) automatically specifying a wire route including a serpentine section within the routing region for connecting the terminals. The serpentine section will include one or more legs sized to ensure that the wire route has the specified wire length. Specifically disclosed is the application of this method to size wiring between two clock buffers in separate and adjacent stages of a clock distribution network. The two clock buffers may be provided in third and fourth stages of the clock distribution network.

Abstract: A system providing capability security for distributed object systems is disclosed. The basic tenet of capability security is that the right to do something to an object (e.g., invoke a particular object's methods) is represented solely by the holding of a reference to that object. In each of the preferred embodiments described herein, an object is presumed to hold legitimately a reference to a particular object only if the object knows some unpublicized (except under the conditions required by capability security) key associated with the particular object. That is, an object's key is required along with the object's reference. So that capability security is preserved when object references are passed between objects in different processes, the object references being passed are encrypted upon transmission and then decrypted upon arrival at their intended destination.

Abstract: An apparatus and method for instantaneously stretching multi-phase clock signals includes a delay line to generate a plurality of multi-phase clock signals. An instantaneous signal stretch logic circuit is connected to the delay line. The instantaneous signal stretch logic circuit transforms the plurality of multi-phase clock signals into stretched multi-phase clock signals in response to a filter capacitor analog signal and a digital stretch signal. Multiple embodiments of the instantaneous signal stretch logic circuit are disclosed. However, each embodiment includes dual current control paths with a single current control path responsive to the digital stretch signal, which is preferably a single bit value.

Abstract: An S8ED system is implemented in a memory system to detect single errors involving one or more bits in a byte of subject data, stored in and retrieved from the memory system. Relationships between the subject data and parity data, which are used to detect errors in the subject data, are defined by a novel check matrix. The novel check matrix includes a number of constituent matrices, each of which includes eight (8) vectors. Each vector of a constituent matrix (i) has a number of elements which is equal to the number of parity bits used to detect errors in the subject data; (ii) is a concatenation of a building block vector, one or more instances of one of two base generating vectors, and one or more instances of the other of the two base generating vectors; and (iii) is distinct from all other vectors of the same constituent matrix.

Abstract: Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. Only the source or drain, not both, have the primary pocket region. An symmetric halo device behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket implant is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.

Abstract: An apparatus and method for enabling a cache controller and address and data buses of a microprocessor with an on-board cache to provide a SRAM test mode for testing the on-board cache. Upon assertion of a SRAM test signal to a SRAM test pin on the microprocessor chip, the cache and bus controllers cease normal functionality and permit data to be written to, and read from, individual addresses within the on-board cache as though the on-board cache is simple SRAM. After the chip is reset, standard SRAM tests can then be implemented by reading and writing data to selected cache memory addresses as though the cache memory were SRAM. Upon completion of the tests, the SRAM test signal is deasserted and the cache and bus controllers resume normal operating functionality. A reset signal is then applied to the microprocessor to reinitialize control logic employed within the microprocessor.

Abstract: Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum.

Abstract: When cache misses occur simultaneously on two or more ports of a multi-port cache, different replacement sets are selected for different ports. The replacements are performed simultaneously through different write ports. In some embodiments, every set has its own write ports. The tag memory of every set has its own write port. In addition, the tag memory of every set has several read ports, one read port for every port of the cache. For every cache entry, a tree data structure is provided to implement a tree replacement policy (for example, a tree LRU replacement policy). If only one cache miss occurred, the search for the replacement set is started from the root of the tree. If multiple cache misses occurred simultaneously, the search starts at a tree level that has at least as many nodes as the number of cache misses. For each cache miss, a separate node is selected at that tree level, and the search for the respective replacement set starts at the selected node.

Abstract: In accordance with the teachings of this invention, a novel voltage regulator is taught which is capable of being formed solely of MOS devices. This eliminates the need to utilize off chip components to form a stand-alone voltage regulator, and avoid the process complexities and increased cost associated with BICMOS fabrication processes.

Abstract: A digital computer system comprises a precise exception handling processor and a control subsystem. The precise exception handling processor performs processing operations under control of instructions. The precise exception handling processor is constructed in accordance with a precise exception handling model, in which, if an exception condition is detected in connection with an instruction, the exception condition is processed in connection with the instruction. The precise exception handling processor further includes a pending exception indicator having a pending exception indication state and a no pending exception indication state. The control subsystem provides a series of instructions to the precise exception handling processor to facilitate emulation of at least one emulated program instruction.

Abstract: A method and an apparatus for reducing data copying overhead associated with protected memory operating systems. In an ATM (Asynchronous Transfer Method) network, the present invention's NIC (network interface circuit) demultiplexes the information in the header of the incoming packet and routes the packet directly to its final destination using the present invention's concept of targeted buffer rings. Thus, instead of having the packet be DMA'd to a buffer in a descriptor ring in the kernel, it may be routed directly to the buffer ring of the destination process.

Abstract: An improved videostream management system. A videostream broadcast or recording includes a relevance level indicator. When a user is unable to view a portion of a videostream, the user may record a highlight videostream. The highlight video is assembled by selecting portions of the videostream for recordation based on the relevance indicator transmitted in conjunction with the basic videostream. The user may then replay highlights of the basic videostream at a later time, without the need for manual editing of the videostream, or for reviewing the entire video stream.

Abstract: A serial data to parallel data converter is disclosed which has the advantage of accurately converting high frequency serial data to parallel data while using clock signals operating at a relatively low frequency. A low bit error rate is achieved by avoiding the use of multiple high speed clock lines typically found in other converters. The simplified circuit design also has the advantage of requiring minimal semiconductor layout area and reduced power requirements. One embodiment includes a buffer, a first data delay line, coupled to receive serial data from the buffer, and a phase lock loop (PLL), coupled to receive serial data from the buffer. A second data delay line is configured as a voltage controlled oscillator (VCO) within the PLL. The PLL locks onto the incoming serial data signal and provides a control signal back to the first data delay line to ensure it is storing serial data bits as they arrive.

Abstract: A program compiler identifies each symbol in a source program that references another program. For each identified symbol, the compiler determines whether the symbol is a reference to a remotely located file or to a locally stored file. If the identified symbol is a reference to a remotely located file, it constructs a file location identifier, such as a URL, for the identified symbol, performs a file location identifier based fetch of the remotely locate file, and ads at least a portion of the fetched file to a set of program code to be compiled if the fetch is successfully performed. If the identified symbol is a reference to a locally stored file, it performs a file fetch for the locally stored file, adding at least a portion of the fetched file to the set of program code to be compiled if the file fetch is successfully performed. If the fetch is unsuccessful, compilation of the source program is aborted.

Abstract: The present invention recognizes that for most functional units, there will rarely be both single and double precision operations in the pipeline at the same time. Accordingly, the present invention eliminates logic for checking whether a register designation is single or double precision for these functional units. Instead, a mode indicator is set to indicate whether the outstanding instructions in the pipeline are single or double precision. If a rare change in precision occurs, the instruction will not be dispatched until the pipeline is empty. The data dependency check logic can thus compare the register designations without knowing whether they are single or double precision.