Abstract: The present invention is a frequency controlled bias generator for stabilizing clock generation circuits. The invention includes a Bias VCO and a clock feedback circuit along with a Phase Frequency Detector for tracking and correcting variations in the frequencies of a High Speed VCO. According to the invention, variations in the frequency of the High Speed VCO are tracked and adjusted across process, temperature, and voltage variations. The invention compares the frequencies of an internal clock generated by Bias VCO with an external clock. When the internal clock frequency is undesirably high or low (based on undesirable variations in process, temperature, and voltage parameters), bias currents provided to the High Speed VCO and the Bias VCO are adjusted such that the frequencies of the Bias VCO and the High Speed VCO are adjusted to offset the variations in process, temperature, and voltage parameters. The bias currents provided to the Bias VCO and the High Speed VCO are matched.

Abstract: A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors to generate the 53.times.53 double-precision product. Delay matching techniques in the binary tree stage and in the final addition stage reduce cycle time. Improved rounding and sticky-bit generating techniques further reduce area and timing. The overall multiplier has a latency of 3 cycles, a throughput of 1 cycle, and a cycle time of 6.0 ns.

Abstract: A system and method is disclosed that provides lightweight non-repudiability for networked computer systems. Each party to a two-party communication maintains hashes on its incoming and outgoing messages. At its discretion, either party can request that the other party commit to the conversation. The second party (if it agrees) then sends signed hashes that third parties can use to verify the content of the conversation. The party requesting the commitment stores its corresponding hashes when it sends the request. If the hashes from both parties are the same for the same positions in their conversation, the two parties can verify that their conversation is error-free. If the sending party also maintains logs of both sides (incoming and outgoing) of the conversation and stores hashes corresponding to the beginning of the logs, the sending party is also able to verify to a third party that the logged portion of the conversation was between the first party and the second party.

Abstract: A method and apparatus is disclosed for interleaving the transfer of pixel data from a dual bank frame buffer to a memory display interface. The interleaved transfer of pixel data to the memory display interface enables upgrade of existing memory display interface designs to higher density VRAM chips in order to increase the capacity of the frame buffer.

Abstract: A paging system communicatively connects a first user initiating a page request using a first telephone to a second user receiving the page request using a second telephone. The paging system includes a paging service transmitter transmitting the page request, and a paging device. The paging device includes a page receiver receiving the page request as a first signal, and a first identification device. The first identification device receives the first signal indicating that the page request was received, and includes an identification transmitter for transmitting a second signal indicating that the second user is ready to be communicatively connected. The paging system includes a second identification device, and receives the second signal transmitted by said first identification device. The second identification device transmits a third signal including a destination number corresponding and addressable to the second telephone.

Abstract: A computer implemented framework method for server benchmarking in a client server environment including a server and at least one client system is provided. The method includes the steps of: activating a benchmark manager application program; activating, by the benchmark manager, a benchmark prime program; activating, by the prime program, a system independent benchmark client program; generating, by the client program, at least one workload request to the server; and measuring the server's response to the at least one workload request.

Abstract: An integrated circuit includes a first metal layer with first layer identification signal writing circuitry connections to produce first metal layer circuit identification signals. The integrated circuit also has a second metal layer with second layer identification signal writing circuitry connections to produce second metal layer circuit identification signals. Logic circuitry in the first metal layer has input connections to the first layer identification signal writing circuitry connections and the second layer identification signal writing circuitry connections. The logic circuitry combines the first metal layer circuit identification signals and the second metal layer circuit identification signals to produce a circuit identification number. The value of the circuit identification number can be changed by altering the first layer identification signal writing circuitry connectors or the second layer identification signal writing circuitry connections.

Abstract: The present invention provides an elegant and simple way to provide mechanisms for invocation of objects by client applications and for argument passing between client applications and object implementations, without the client application or the operating system knowing the details of how these mechanisms work. Moreover, these mechanisms functions in a distributed computer environment with similar ease and efficiency, where client applications may be on one computer node and object implementations on another. The invention includes a new type of object, termed a "spring object," which includes a method table, a subcontract mechanism and a data structure which represents the subcontract's local private state.

Abstract: A multi-tier cache system and a method for implementing the multi-tier cache system is disclosed. The multi-tier cache system has a small cache in random access memory (RAM) that is managed in a Least Recent Used (LRU) fashion. The RAM cache is a subset of a much larger non-volatile cache on rotating magnetic media (e.g., a hard disk drive). The non-volatile cache is, in turn a subset of a local CD-ROM or of a CD-ROM or mass storage device controlled by a server system. In a preferred embodiment of the invention, a heuristic technique is employed to establish a RAM cache of optimum size within the system memory. Also in a preferred embodiment, the RAM cache is made up of multiple identically-sized sub-blocks. A small amount of RAM is utilized to maintain a table which implements a Least Recently Used (LRU) RAM cache purging scheme. A hashing mechanism is employed to search for the "bucket" within the RAM cache in which the requested data may be located.

Abstract: A method facilitating modification of an application's graphical user interface (GUI), particularly by application end-users. In particular, the method permits modification of the application GUI, without having to specify widgets required for the modified GUI, and without having to modify or add callback routines. Thus, users can tailor the application GUI to suit their needs without having experience in GUI development (and, in particular, with the cumbersome and error-prone tasks of widget-specification and callback programming). Elimination of the need to modify/expand the set of callback routines permits end-users to realize application GUI changes without having to form a new application executable. Thus, user-driven application GUI changes can be achieved without user access to the application source code and without the application developer's involvement.

Abstract: A method and apparatus for adding and deleting data in a plurality of heaps stored in memory, where the ordering of the data in the heaps is maintained across the heaps as the additions and deletions are performed. Not all entries in the heaps have a corresponding entry in all of the other heaps, but the ordering of the data in the heaps is in accordance with an order dependent list stored in memory. Such ordered heaps are useful for example, in a incremental linker software program.

Abstract: A programmable digital frequency multiplier includes either a delay locked loop with an input clock or a ring oscillator which generates multiple phase delayed clock signals having a common frequency equal to that of the input clock and a corresponding number of equidistant phases. In the delay locked loop, a phase comparator compares the phase of the input clock as received by the first inverter circuit with the phase of the output of the last inverter circuit and generates an error signal which is used as a circuit bias control signal for each of the inverter circuits, thereby controlling the phase delay through each inverter circuit. The multiple inverter circuit output signals are individually gated in separate NOR gates with a corresponding number of frequency programming bits.

Abstract: Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact. The enhanced quotient digit selection logic chooses a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen.

Abstract: A scanning transmissometer is disclosed for use with a large number of reflectors for detecting dense, but very localized patches of fog to permit warnings to be given to drivers in time to avoid accidents. Reflectors utilized to reflect the laser beam from a scanning transmissometer are heated to remove condensation before measurements of transmissivity are taken. In some implementations, heaters for reflectors are initiated upon detection of a prescan illumination of the reflector by a laser beam and a timer is utilized to turn off heating, once condensation has been dispersed.

Abstract: A computer-implemented method and system for of retrieving information. A first file of information is received which includes a first markup language to identify contents of the information. Responsive to the receiving the first file of information, the first file of information is parsed to generate a list of profiles, and at least one corresponding topic for each of the list of profiles. A second file in a second markup language is created containing the list of the profiles and at least one corresponding third file is created in a third markup language for the at least one corresponding topic for each of the list of profiles. The second file contains anchors referencing each at least one corresponding third file, and first markup instances in the first file of information are converted to second markup instances in either the second file or the third file.

Abstract: CSMA/CD is used to implement flow control in a full-duplex Ethernet network in a lossless fashion. Uniquely identifiable flow control transmit on/off ("XON/XOFF") messages are transmitted, preferably during IPG, by a receiving station about to be congested to the transmitting station whose data output is to be controlled. The transmitting station physical layer receives and decodes these messages. If XOFF is recognized, the transmitting station continuously asserts CRS to its MAC layer at the MII, regardless of the prior CRS current state. CRS is continuously asserted until the receiving station transmits an XON flow control signal, indicating its ability to accept further data. During CRS assertion, the transmitting station defers transmission, e.g., is flow controlled. The MAC layer is slightly modified (but is still backward compatible with half-duplex networks) to provide separate transmit deferral receive data frame mechanisms using separate and independent input status signals, namely CRS and RX.sub.

Abstract: A system and method for computer operation. An object to be pointed to in a user's computer display (109) is indicated with an animated pointer icon (113). In a computer network, such as the Worldwide Web, a pointer is transmitted from one user to another user (114) via an improved protocol. A graphical design (201) of a computer icon is also disclosed.

Abstract: A cascoded cmos differential delay element is described. The delay element provides a controlled delay useful in forming voltage controlled oscillators or other circuits. The delay element provides high gain enabling it to be useful in multistage delay element circuits. The circuit described includes cascoded complementary differential amplifiers and replicated bias clamps.

Abstract: A computer system having virtual memory that can be mapped using multiple page sizes onto logically addressable physical memory. An intermediate addressing scheme permits the mapping of several non-contiguous small pages in physical memory onto a bigger sized virtual memory page. Rather than translating a virtual address directly into a physical address, a virtual address is translated into an intermediate address that may or may not be a physical address. If the virtual page is backed by physical memory that is contiguous and aligned on a proper boundary for the page size, then the intermediate address will be the physical address and no second translation is required. If the intermediate address is not a physical address, it is then translated into a physical address. This is the case where a big page in virtual memory is backed by more than one smaller page in physical memory.

Abstract: A dependency checking apparatus includes a scoreboard which records destination operands of instructions outstanding within the pipeline of a microprocessor. Each single precision register maps to an indication within the scoreboard. Each double precision register which does not overlap with single precision registers maps to an indication within the scoreboard. Double precision registers which overlap single precision registers map to the set of indications corresponding to the overlapping single precision registers. Dependency checking for a source operand is performed by forming a first set of indications corresponding to the double precision registers and a second set of indications corresponding to the single precision registers, then selecting a dependency indication from these sets of indications in response to the source precision and the source register address.