Abstract: The present invention pertains to standoff devices used to hold a circuit board a fixed distance from a mounting surface such as another circuit board. The present invention divides the standoff into two interacting members. The first member has a base and two arms disposed to define a receiving slot between the two arms. The second member is comprised of a head portion, a tapered portion, and a tongue portion. The second member is slidably disposed within the receiving slot of the first member, and is capable of being locked into place in two distinct locking positions within this receiving slot. By sliding the second member from the first locking position to the second locking position, the standoff is locked into place between the circuit board and the mounting surface. The present invention discloses a secure locking system utilizing locking projections and cooperating depressions to accomplish this locking function.

Abstract: A method and apparatus for saving memory space in a buffer whereby the valid bit in the entry of the translation lookaside buffer for a cache memory is collapsed into one of the level bits indicating the length of the virtual address. During the lookup of the translation lookaside buffer, the virtual address in each entry is compared with the virtual address from the CPU if the level/valid bit is set, i.e. the entry is valid. If the level/valid bit is not set, then no compare takes place and the lookup continues to the next entry. The length of the virtual address to be compared is further determined by the status of the remaining level bits.

Abstract: A high reliability phase-locked loop (PLL) is disclosed having a hyperactivity detection and correction circuit (HDC) to oversee the oscillator and the phase and frequency detector (PFD), and having a PFD reset gate that performs the required logic function to reset the PFD while not being vulnerable to an internal PFD race condition that plagues prior art phase-locked loop circuits. The HDC senses the oscillator control and signals an oscillator reset should the oscillator control rise to an abnormally high level above a predetermined limit while the PFD is not detecting the feedback signal. The oscillator reset signal then slowly propagates through an asymmetrical delay line and resets the oscillator control to a predetermined reset state. While the oscillator control is being reset, the HDC continues to monitor the oscillator control, and de-asserts the oscillator reset when the oscillator control drops to the predetermined reset state.

Abstract: An optimized integral heat pipe and electronic circuit module arrangement is described. A ceramic multi-chip module bearing electronic circuit components has applied to the side opposite the electronic circuit components preparatory metallization and a thermal wick. A heat pipe evaporator chamber and condenser assembly is attached to the multi-chip module and wick assembly. A suitable working fluid is introduced into the vapor chamber and the vapor chamber hermetically sealed. Application of the thermal wick to the heat producing multi-chip module eliminates the thermal impedance contributed by thermal transmission media used in prior art heat pipe assemblies, permitting a doubling of heat flux from the multi-chip module to the heat pipe evaporator.

Abstract: In the system of the present invention, an event driven journaling mechanism which is not dependent on the timing of execution of processes is implemented. Special events, referred to as synchronization events, mark locations, referred to as synchronization points, in the journal file of events where previously initiated processing must be completed before initiating the subsequent process. The synchronization points are located between processes which are exchanging state. The synchronization events are put into the journal file during the recording phase. On playback, the journaling mechanism waits for a synchronization event to occur before proceeding to the next action in the journal file and initiating subsequent execution of the process.

Abstract: A primary, a secondary, and a tertiary cache, and a floating point pipeline having optimized complimentary characteristics are provided to a computer system for executing floating point instructions. The primary cache is direct mapped and having n.sub.1 cache lines, each having a cache line size of m.sub.1 floating point data word(s) and an access time of t.sub.1 clock cycle(s), where m.sub.1 and t.sub.1 are both small integer greater than or equal to 1. The secondary cache is fully associative having n.sub.2 cache lines, each having a cache line size of m.sub.2 floating point data words and an access time of t.sub.2 clock cycles, where n.sub.2 is a small integer, m.sub.2 is greater than m.sub.1, and t.sub.2 is a small integer greater than t.sub.1. The tertiary cache has n.sub.3 cache lines, each having a cache line size of m.sub.3 floating point data words and an access time of t.sub.3 clock cycles, where m.sub.3 is greater than m.sub.2 and t.sub.3 is a small integer greater than t.sub.2.

Abstract: A method and apparatus for loading a data value for a future LOAD instruction in a microprocessor by predicting the LOAD instruction's effective address. At each occurrence of a LOAD instruction, the effective address used is stored in a memory array which stores a last effective address and a next-to-last effective address. At a specified period before each LOAD instruction, the microprocessor loads a data value from a predicted effective memory address computed from the memory array. The predicted effective memory address is equal to the last effective address plus the difference between the last effective address and the next-to-last effective address. If the predicted effective address equals the actual effective address of the future LOAD instruction, the loaded data value is used.

Abstract: A method and apparatus are provided for enabling a computer that is capable of running programs utilizing different address sizes to run those programs without having to modify the computer's hardware. A mask register is used to identify bits of a sum of register addresses that are valid for the program that is running. The number of valid bits in the register mask can be changed to correspond to the addressable memory size for different programs.

Abstract: A computer integrated circuit arrangement including flip-flop circuits, buffers, and combinatorial circuit elements in which the flip-flop circuits are arranged in rows with buffers which may be connected to drive signals to those flip-flop circuits, the flip-flop circuits having conductors designed to carry global signals arranged to traverse the width of the flip-flop circuits and provide input and output terminals to match input and output terminals of adjacent flip-flop circuits.

Abstract: An apparatus and method are disclosed for switching the arrays of parallel memory data structures upon the detection of defects in a memory storage device. To date, redundancy has been implemented using duplicate arrays connected to laser zappable fuses. The use of laser zappable fuses imposes restrictive technology constraints. In particular, to avoid damage to surrounding circuity when a fuse is "zapped," considerable space must be allowed between each fuse and other fuses or other unrelated circuitry. The present invention uses only two extra parallel arrays to correct for any open or short defects in a parallel memory data structure, and does it with a nearly constant array length as the original arrays. The redundant arrays as well as the original arrays are connected to toggle switches. Upon encountering any open or short in the one or more data paths, the toggle switches coupled to the open or short are "flipped" to connect to the adjacent data paths in a cascading fashion.

Abstract: An extraction tool that provides for easy removal of a SIMM from a connector while preventing damage to the SIMM and the connector. The extraction tool is composed primarily of a handle portion and two arms. Each arm has a pin that couples to the holdes in a SIMM. Each arm is further comprised of an elbow portion to allow for pivoting motion of the extraction tool in order to pry a SIMM from its connector. Contact edges are provided on each arm to aid in positioning the extraction tool upon the upper edge of a connector. Each arm of the extraction tool has a chamfer surface to provide for proper coupling of a SIMM connector and to the holes in the ends of a SIMM while the SIMM is installed.

Abstract: A method and apparatus for cost based heuristic instruction scheduling for a pipelined processor is disclosed which has particular application to compile time instruction scheduling after code generation. The method and apparatus schedules instructions of an instruction block one at a time, based on the lowest total cost among all the current eligible free instructions. The total cost of each of the current eligible free instructions is computed based on the weighted sum of a plurality of cost heuristics. The cost heuristics used in the preferred embodiment comprise a resource dependency cost, a data dependency cost, a dependency wait cost, a dependent cycle cost, a floating point ratio cost, a store ratio cost and a floating point queue cost. Additionally, in the preferred embodiment, a number of the cost heuristics are modeled by a processor model. As a result, improved overall effectiveness in speeding up the execution time of an instruction block is achieved.

Abstract: In the method and apparatus of the present invention a file to be added to the database is given a unique name that is dependent upon the contents of the file such that, when the contents of the source file changes, the name of the database component file to be added to the database also changes. Conversely, if two files of the same name have the same information contained therein, the same file name will be generated and the duplication of information in the database is prevented by providing a simple test that checks for the existence of the name of the database file before the generation and addition of the new file to the database. If the file name exists in the database, information is already contained in the database and the file is not generated and added to the database information. Preferably the name of the file is generated by computing a hash value from the contents of the file concatenating the hash value to the name of the source file.

Abstract: The distance between the intensity value of the base value (that is, the closest quantized intensity value less than the input intensity value) and the input intensity value is adjusted according to a mapping function between the size of the interval between the intensity values of the base value and the base value +1 (i.e., the next larger quantized intensity value) and the range of values in the dither matrix. By adjusting the distance between the base value and the input intensity value, the correct proportion of base values and base values +1 is maintained regardless of the difference in size of the interval and the range of the dither matrix, thereby insuring that the intermediate intensity values between quantized values are accurately simulated.

Abstract: A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller. Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.

Abstract: A quick connect modular unit retainer assembly for easily installing or removing a modular unit such as a disk drive in a computer housing. Threaded inserts having elastomer sleeves are mounted to the modular unit. The insert assemblies are inserted first vertically, and then horizontally, into L-shaped channels on bosses projecting upward from the computer base. Cooperating fingers extending downward from a pivoted computer cover are maneuvered into the L-shaped channels adjacent to the insert assemblies, thereby locking the insert assemblies, and hence modular unit, into place.

Abstract: A high reliability phase-locked loop (PLL) is disclosed having a hyperactivity detection and correction circuit (HDC) to oversee the oscillator and the phase and frequency detector (PFD), and having a PFD reset gate that performs the required logic function to reset the PFD while not being vulnerable to an internal PFD race condition that plagues prior art phase-locked loop circuits. The HDC senses the oscillator control and signals an oscillator reset should the oscillator control rise to an abnormally high level above a predetermined limit while the PFD is not detecting the feedback signal. The oscillator reset signal then slowly propagates through an asymmetrical delay line and resets the oscillator control to a predetermined reset state. While the oscillator control is being reset, the HDC continues to monitor the oscillator control, and de-asserts the oscillator reset when the oscillator control drops to the predetermined reset state.

Abstract: The method of the present invention includes steps wherein a circuit designer, using standard computer assisted design (CAD) tools, designs a circuit which may include multi-cycle paths (MCPs). The designer inserts a conceptual circuit element, referred to as a "path breaker" into multi-cycle paths, such that the result is to convert all multi-cycle paths into single cycle paths. The designer then utilizes functional simulation software to edit the circuit design. To the simulator, a path breaker appears to be a latch in which the latch output goes to an unknown state when the input changes, and remains so until the output has been clocked and is equal to the input. Traditional logic synthesis is then performed on the circuit such that a net list is generated which includes the path breakers. Based on the net list, a post processor determines where in the circuit multi-cycle paths exist and generates a net list without path breakers, as well as a list of the multi-cycle paths.

Abstract: A method and apparatus for implementing a class hierarchy of objects in a hierarchical file system is disclosed, which does not require the support of additional file attributes by the hierarchical file system, and has particular application to object oriented programming in window-based computer systems. The class hierarchy comprises a root class, a plurality of classes and a plurality of class instances. The root class is implemented with a hierarchy of root class directory and root class files. Each class is implemented with a hierarchy of class directories and class files comprising the class methods, and the initial values of the class instance variables. Each class instance is implemented with a hierarchy of class instance directory and class instance files comprising the class instance variables. Each hierarchy of directories and files also comprises a path file. The content of these path files are logically related to each other, based on their class' relationships.

Abstract: An asynchronous form of pipeline processor has a storage capability for partially processed data. When the processor is empty, it functions as a combinatorial circuit producing resultant data processed as desired. As necessary, the processor registers data, however, it continues to advance other data as rapidly as possible. A control unit individually provides binary control signals to a plurality of processing apparatus to maintain order with respect to processing and storing data. Switching structures controlled by the control unit along with amplifiers are provided at the input and output of individual processors to set the processing apparatus to process or store data. Processing several sets of data simultaneously while preserving proper order enables the system to do logic and arithmetic processing at a relatively high speed.