Patents Assigned to Sun Microsystems
  • Patent number: 7484195
    Abstract: A method for performing sensitivity analysis on a circuit design is provided. The method initiates with identifying a partition of the circuit design. The method includes determining whether the partition belongs to a sensitivity graph, where the sensitivity graph represents a relationship between variables and parameters of the partition. If the partition belongs to the sensitivity graph, then the method includes, applying linear matrix factors to provide a solution to a system of linear equations and multiplying the solution by a vector to derive sensitivities for the circuit design.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: January 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventor: Alexander Korobkov
  • Patent number: 7481116
    Abstract: An apparatus for measuring vibration of a fan includes a frame having an opening for enclosing a fan; a plurality of accelerometers disposed on the frame; and an elastic support for supporting the frame. An apparatus for measuring fan vibration includes a frame having an opening for enclosing a fan; a plurality of accelerometers disposed on the frame. The plurality of accelerometers output a signal to the signal-analyzing device and at least three of the plurality of accelerometers are disposed on a different surface of the frame from each other. The apparatus for measuring fan vibration includes a mounting block that allows the fan to be secured in the opening of the frame and an elastic support for supporting the frame. A method of measuring fan vibration includes disposing a plurality of accelerometers on a frame; mounting a fan within the frame; turning on the fan; and outputting a signal from each of the plurality of accelerometers to a signal-analyzing device.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: January 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventor: Jay K. Osborn
  • Patent number: 7483442
    Abstract: An Infiniband switch can be provided. The switch can have an input port logic unit for determining an output virtual lane for a received packet and for storing a descriptor of the determined output virtual lane in a packet field not protected by a checksum field of the packet. The switch can also have a routing unit for transferring the received packet to an output port corresponding to the determined output virtual lane. Additionally, the switch can have an output port logic unit for simultaneously checking the integrity of the packet transferred through the routing unit and calculating a new value for the checksum with the descriptor moved to a correct packet field, which field is included in the calculation of the checksum.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: January 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Ola Torudbaken, Hans Rygh, Steinar Forsmo, Morten Schanke
  • Patent number: 7483930
    Abstract: One embodiment of the present invention provides a system that facilitates identifying roots for a garbage-collection operation in a computer system that supports an object-addressed memory hierarchy. In order to identify roots, the system first looks up an object table entry that corresponds to an object in an object cache, wherein the object table entry contains an evicted bit, which is set when any part of the modified object is evicted from the object cache, and a corresponding physical address for the object in main memory. Next, the system determines if the evicted bit is set in the object table entry, and if so, examines the object corresponding to the object table entry to determine if the object contains references to the target area in the object heap that is being garbage collected. If so, the system uses the references as roots for a subsequent garbage-collection operation of the target area.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: January 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Gregory M. Wright, Matthew L. Seidl, Mario I. Wolczko
  • Patent number: 7483248
    Abstract: One embodiment of the present invention provides a system that detects changes in power-supply current within an integrated circuit (IC) chip. During operation, the system monitors an induced current through a detection loop. This detection loop is situated at least partially within the IC chip in close proximity to a power-supply current for the IC chip, so that a change in the power-supply current changes a magnetic field passing through the detection loop, thereby inducing a corresponding current through the detection loop. The system then generates a control signal based on the induced current, so that changes in the power-supply current cause the control signal to change. In addition, the system uses the control signal to control circuits within the IC chip.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: January 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Ronald Ho, Robert J. Drost, Arthur R. Zingher
  • Patent number: 7484055
    Abstract: A method for faster handling of state change notifications in a storage network such as storage area network (SAN). The method includes receiving a state change notification at a host. The notification is processed to identify a target device affected by a state change. The method includes cleaning an input/output (I/O) resource of the host of I/O operations associated with the target device. A new session request is transmitted from the host to the target device, such as the next communication from the host after receipt of the notification. The cleaning of the host's I/O resources may include killing or abandoning pending I/O operations related to the target device and may also include halting or stopping additional or future I/O operations to the target device. The method includes operating the affected target device to acknowledge the new session request and initiate a new session that includes refreshing target I/O resources.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: January 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Sumit Gupta, Deepak M. Babarjung, Sajid Zia
  • Patent number: 7483932
    Abstract: Methods, systems, and articles of manufacture consistent with the present invention compute a multidimensional fast Fourier transform of an original matrix having rows and columns of data. The original matrix is divided into a number of blocks of data, each block including at least one datum, the number of rows of data in each block being less than a total number of rows of data in the original matrix. A one-dimensional partial fast Fourier transform of each block in a row of blocks is computed. A result of the computations is stored in a resultant matrix having rows and columns. The resultant matrix is transposed to a transposed matrix having rows and columns. While transposing the resultant matrix, one-dimensional partial fast Fourier transforms of each block of subsequent rows of blocks are simultaneously computed, one row of blocks at a time, until one-dimensional partial fast Fourier transforms are computed for each block.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: January 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventor: Michael L. Boucher
  • Patent number: 7483811
    Abstract: A system that uses statistical techniques to selectively transmit data from a sensor. During operation, the system receives a sequence of quantized values from the sensor. The system then determines whether a distribution for the sequence of quantized values indicates that the sensor is observing a real event. If so, the system transmits sensor data for the real event to a receiver.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: January 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Keith A. Whisnant, Kenny C. Gross
  • Publication number: 20090022160
    Abstract: Embodiments of a scheduler for a switch, where the switch is configured to couple input ports to output ports are described. During operation, the scheduler may determine a schedule based on a group of requests, associated with multiple data streams, that are received for the output ports of the switch, where the schedule matches input ports to output ports of the switch for a given data cell time. Note that the schedule may be determined using an arbitration technique during a time interval. Moreover, the scheduler may assign an additional request, which was received at a time that precedes a current time by less than the time interval, to a portion of the switch which is available in the schedule, thereby reducing a latency of the scheduler.
    Type: Application
    Filed: June 9, 2008
    Publication date: January 22, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Hans Eberle, Nils Gura, Wladyslaw Olesinski, Andres Mejia
  • Publication number: 20090024564
    Abstract: A method for accessing a file system that includes creating a document index for an active document, identifying a similarity score for each of a plurality of stored documents to generate a list of similar documents, wherein the similarity score is computed by comparing the document index for the active document with a search index for the plurality of stored documents, and displaying the list of similar documents in a file system interface.
    Type: Application
    Filed: July 19, 2007
    Publication date: January 22, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Stephen J. Green, Jeffrey L. Alexander, Paul B. Lamere
  • Patent number: 7480609
    Abstract: A system for applying distributed software simulation techniques to hardware emulation may include a first hardware emulator mounted on a first expansion board at a first host, and a second hardware emulator mounted on a second expansion board at a second host. The first hardware emulator may be configured to emulate a first portion of a system under test, and the second hardware emulator may be configured to emulate a second portion of the system under test, and the first and second hardware emulators may coordinate an emulation of the system under test using one or more messages, i.e., a coordination of an emulation of the system under test may be accomplished using communications between the first and second hardware emulators.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: January 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Carl Cavanagh, Steven A. Sivier
  • Patent number: 7478741
    Abstract: An apparatus and method for non-destructive solder interconnect integrity monitoring that can detect existing fracture damage, identify new or incipient fractures, and be implemented across multiple component configurations. Said components can be implemented to detect, on a continuous basis, solder interconnect fractures as they occur during actual end-use, throughout the lifecycle of monitored components, rather than relying on a one-time electrical check prior to shipment.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: January 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventor: Keith G. Newman
  • Patent number: 7480900
    Abstract: A system and method for mapping software components (e.g., source files, binary files, modules) to test cases that test the components and providing rating information regarding each test case's effectiveness against its tested components. Each test case is applied to test a corresponding subset of the components, during which data are gathered (e.g., amount or elements of a component that were tested, which components were tested, time). Each test case is applied separately so that correlations between each test case and the corresponding subset of the software components can be recorded (and vice versa). A rating is generated to indicate how completely or effectively a test case covers a software component. A bipartite graph and/or other data structures may be constructed to map test cases to the software components they test, and vice versa.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: January 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Charles Jianping Zhou, Teh-Ming Hsieh
  • Patent number: 7480291
    Abstract: In an embodiment of the present invention, a first communication packet is assigned to a first communication data structure that is unique to a first connection comprising the first communication packet. A first event list is selected from a database based on a classification of the first communication packet. The first event list identifies a first plurality of communication modules (e.g., socket layer, TCP layer, IP layer, IP security layer, firewall layer, etc.) and an ordering thereof, specific for the needs of the first connection. The first communication packet is processed through the first plurality of communication modules based upon the ordering specified in the first event list. A reference contained in the data structure marks the current packet position though the plurality of communication modules.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: January 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Sunay Tripathi, Erik Nordmark
  • Patent number: 7480684
    Abstract: A method for locating a root block in file system metadata, includes traversing the file system metadata to locate a leaf block, wherein the leaf block comprises a plurality of root blocks and at least one of the plurality of root blocks is unallocated, allocating the at least of one the plurality of unallocated root blocks to obtain an allocated root block, wherein the leaf block is associated with a fill count and the fill count is less than a maximum fill count of the leaf block.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: January 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Jeffrey S. Bonwick, William H. Moore, Matthew A. Ahrens
  • Patent number: 7480735
    Abstract: A system and method for routing between nodes in a network or subnet. An end node is associated with multiple identifiers for routing purposes, and therefore multiple paths may exist between two end nodes. Network nodes and components (e.g., switches) are grouped into fault zones. Each physical enclosure of network entities may comprise a separate fault zone. For each zone through which a path between two nodes passes, a weight is calculated equal to the number of paths between the nodes that traverse that zone. Path weights are calculated for each path between the nodes, equal to the sum of the weights of each zone in the path. To improve network fault tolerance, new paths may be designed to avoid fault zones and existing paths with high weights. Instead of fault zones, other criteria may be used to assign weights, such as mean time between failures (MTBF), cost, speed, etc.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: January 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Jeremy N. Shapiro, Stephen A. Jay
  • Patent number: 7480816
    Abstract: A cluster or group of cooperating systems may implement failure chain detection and recovery. The group may include multiple nodes and each node may include a group management services (GMS) module that in turn may include a group communications mechanism to detect cluster membership events. Each GMS module may maintain an identically ordered view of the current group membership. When a member of the group fails, the member that joined the group immediately after the failed member, according to respective join times, may be selected to perform recovery operations for the failed member. If a group member fails while performing recovery operations for another failed member, the next member in the group (according to respective join times) may be selected to perform recovery for that node and may also perform recovery operations for the original failed node as well.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: January 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Masood S. Mortazavi, Shreedhar Ganapathy
  • Patent number: 7480770
    Abstract: In one embodiment, a node for a multi-node computer system comprises a coherence directory and a coherence controller. The coherence directory comprises a plurality of entries, wherein each entry corresponds to a respective coherence unit and stores a state identifying which nodes in the computer system are storing a copy of the coherence unit and further identifying a coherence state of the coherence unit according to a coherence protocol implemented in the computer system. Coupled to the directory and coupled to receive a first request for a requested coherence unit having a first entry in the coherence directory, the coherence controller is coupled to receive a second request for the requested coherence unit. The coherence controller is configured to selectively initiate coherence activity for the second request, if coherence activity for the first request is not yet complete, dependent on a type of the second request.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: January 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: HÃ¥kan E. Zeffer, Anders Landin
  • Patent number: 7480873
    Abstract: One embodiment of the present invention provides a system that facilitates manipulating a 2D window within a three-dimensional (3D) display model. During operation, the system receives an input from a 2D pointing device, wherein the input specifies a 2D offset within a 2D display, and wherein the 2D display provides a view into the 3D display model. Next, the system uses the 2D offset to move a cursor to a position in the 2D display, and then determines if the cursor overlaps a window within the 3D display model. If so, the system determines a 2D position of the cursor with respect to a 2D coordinate system for the window, and communicates this 2D position to an application associated with the window. This enables a user of the 2D pointing device to interact with the application.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: January 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventor: Hideya Kawahara
  • Patent number: 7480782
    Abstract: Reference updating in a sliding compaction garbage collector may involve maintaining, for each logical region of the heap to be compacted, values that represent the range of addresses referenced by individual regions of the heap. For example, a highest-referenced address (HRA) represents the maximum address referenced by any object references in the respective region. Similarly, a lowest-reference address (LRA) represents the minimum address referenced by a region. When updating references during compaction, if the HRA and/or LRA for a particular region indicate that all references within the region point to addresses within a region of memory that will not be relocated during compaction, such as a dense prefix, the references with the particular region need not be updated. Maintaining HRAs and/or LRAs for region of heap memory may simplify determining whether or not references within individual regions require updating.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: January 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventor: Alexander T. Garthwaite