Patents Assigned to SUNEDISON
  • Publication number: 20170256439
    Abstract: Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.
    Type: Application
    Filed: July 28, 2016
    Publication date: September 7, 2017
    Applicant: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Hui Wang, Vandan Tanna, Tracy Michelle Ragan, James Raymond Capstick
  • Publication number: 20170234960
    Abstract: A method of preparing an iron-implanted semiconductor wafer for use in surface photovoltage iron mapping and other evaluation techniques. A semiconductor wafer is implanted with iron through the at least two different regions of the front surface of the semiconductor at different iron implantation densities, and the iron-implanted semiconductor wafer is annealed at a temperature and duration sufficient to diffuse implanted iron into the bulk region of the semiconductor wafer.
    Type: Application
    Filed: September 16, 2015
    Publication date: August 17, 2017
    Applicant: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Igor Rapoport, Robert James Crepin, Patrick Alan Taylor
  • Patent number: 9727045
    Abstract: A method and system for computerized coordination of multiple operations to be performed by components of machines are provided. The computer system includes a memory device for storing data and a computer-controlled machine that includes a processor in communication with the memory device wherein the processor is programmed to read a recipe file from the memory device, the recipe file including operating parameter values for controlling the operation of the machine, extract a name of a meta-recipe file from the recipe file, the meta-recipe file including a first portion including parameter properties of operating parameter values used by the meta-recipe file, receive values for the meta-recipe having the parameter properties specified in the first portion, and operate the machine using code from a second portion of the meta-recipe and the received values.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 8, 2017
    Assignee: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
    Inventors: Benno Orschel, Mike Wolfram
  • Publication number: 20170178890
    Abstract: Methods for polishing semiconductor substrates are disclosed. The finish polishing sequence is adjusted based on a measured edge roll-off of an analyzed substrate.
    Type: Application
    Filed: December 21, 2016
    Publication date: June 22, 2017
    Applicant: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Alex Chu, Hsin-Yi Chi, Francis Hung, Jones Yang, H.J. Chiu, J.W. Lu
  • Patent number: 9665931
    Abstract: Methods and systems for use in detecting an air pocket in a single crystal material are described. One example method includes providing a matrix including a plurality of data units, the plurality of data units including image data related to a region of interest of the single crystal material; determining, by a processor, a difference between data units of the matrix and a corresponding data unit of the matrix, wherein the corresponding data unit is defined by a first operation of the matrix; calculating, by the processor, a first index value based on the differences of the corresponding data units; and identifying an air pocket within the single crystal material based on the first index value and a predetermined threshold.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: May 30, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventor: John F. Valley
  • Patent number: 9634098
    Abstract: A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 25, 2017
    Assignee: SunEdison Semiconductor Ltd. (UEN201334164H)
    Inventors: Robert J. Falster, Vladimir V. Voronkov
  • Patent number: 9634689
    Abstract: A computer-implemented method for arranging numeric data for compression is described. The method is implemented using a computing device in communication with a memory and a measurement device. The method includes receiving, by the computing device and from the measurement device, numeric data that includes a sequence of numbers, each number including at least a first byte followed by a second byte. The method additionally includes arranging the first bytes into a first contiguous set, arranging the second bytes into a second contiguous set, and storing the first contiguous set and the second contiguous set in a file in the memory, such that the first contiguous set is contiguous with the second contiguous set.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: April 25, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventor: Markus Jan Peter Siegert
  • Patent number: 9601395
    Abstract: In one aspect, a method of predicting warp in a plurality of wafers after an epitaxial layer deposition process is provided. The method includes receiving, by a processor, a measured resistivity of a first wafer of the plurality of wafers, receiving, by the processor, a measured shape of the first wafer after at least one of a grinding process and an etching process, and calculating, using the processor, a change in wafer shape during the epitaxial layer deposition process. The method further includes superposing, using the processor, the calculated shape change onto the measured shape of the first wafer to determine a post-epitaxial wafer shape and calculating, using the processor, a post-epitaxial warp value based on the determined post-epitaxial wafer shape.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 21, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Sumeet S. Bhagavat, Roland R. Vandamme
  • Patent number: 9589079
    Abstract: A method for designing a photovoltaic (PV) system is implemented by a design automation computer system. The method includes receiving a set of site data, receiving a system type selection, receiving a plurality of system component selections, receiving a plurality of PV layout preferences, determining a PV module layout by iteratively applying a first layout algorithm to the set of site data and the plurality of PV layout preferences, the PV module layout defining a placement of a plurality of PV modules of a PV system, determining a structural layout, an electrical design, and an electrical layout based on the PV module layout, determining a bill of materials based on the PV module layout, the structural layout, and the electrical layout, and designing the PV system using the structural layout, the electrical design, the electrical layout, the PV module layout, and the bill of materials.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: March 7, 2017
    Assignee: SunEdison, Inc.
    Inventors: Andrew Joseph Morse, Nagendra Srinivas Cherukupalli, Ravi Ranganathan, Krishnan Ramagopal
  • Patent number: 9583364
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 28, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 9583363
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 28, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20170053826
    Abstract: Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.
    Type: Application
    Filed: July 28, 2016
    Publication date: February 23, 2017
    Applicant: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Hui Wang, Vandan Tanna, Tracy Michelle Ragan, James Raymond Capstick
  • Patent number: 9566687
    Abstract: A polishing head assembly for single side polishing of silicon wafers is provided. The polishing head assembly includes a polishing head and a cap. The polishing head has a recess along a bottom portion, the recess having a recessed surface. The cap is positioned within the recess, and has an annular wall and a floor extending across the annular wall. The floor is spaced from the recessed surface to form a chamber therebetween. The chamber is configured to be pressurized for deflecting the floor. The annular wall is attached to the polishing head with an adhesive.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: February 14, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Peter Albrecht, Sumeet Bhagavat, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
  • Publication number: 20170025306
    Abstract: Methods for preparing silicon-on-insulator structures and related intermediate structures are disclosed. In some embodiments, a single crystal silicon seed crystal is bonded to an amorphous silicon layer disposed on a substrate and the amorphous layer is crystallized to form a monocrystalline silicon layer.
    Type: Application
    Filed: June 24, 2016
    Publication date: January 26, 2017
    Applicant: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Gang Wang, Jeffrey L. Libbert, Qingmin Liu, Alex Usenko, Shawn George Thomas
  • Publication number: 20170025307
    Abstract: Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure.
    Type: Application
    Filed: January 9, 2015
    Publication date: January 26, 2017
    Applicant: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Michael J. Ries, Jeffrey Louis Libbert, Charles R. Lottes
  • Publication number: 20170016141
    Abstract: Production of silicon ingots in a crystal puller that involve reduction in the formation of silicon deposits on the puller exhaust system are disclosed.
    Type: Application
    Filed: July 17, 2015
    Publication date: January 19, 2017
    Applicant: SUNEDISON, INC.
    Inventors: Tirumani N. Swaminathan, Jihong Chen
  • Publication number: 20170016142
    Abstract: Production of silicon ingots in a crystal puller that involve reduction of the erosion rate at the crucible contact point are disclosed.
    Type: Application
    Filed: July 17, 2015
    Publication date: January 19, 2017
    Applicant: SunEdison, Inc.
    Inventors: Jihong Chen, Tirumani N. Swaminathan
  • Patent number: 9527752
    Abstract: Methods for producing aluminum trifluoride by acid digestion of fluoride salts of alkali metal or alkaline earth metal and aluminum, optionally, in the presence of a source of silicon; methods for producing silane that include acid digestion of by-products of silane production to produce aluminum trifluoride.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: December 27, 2016
    Assignee: SunEdison, Inc.
    Inventors: Puneet Gupta, Satish Bhusarapu
  • Publication number: 20160348983
    Abstract: Heat exchange apparatus and, particularly, heat exchangers having a baffled cooling jacket are disclosed. Methods for using the exchangers including methods that involve cooling an effluent gas produced from a fluidized bed reactor for producing polycrystalline silicon are also disclosed.
    Type: Application
    Filed: May 28, 2015
    Publication date: December 1, 2016
    Applicant: SUNEDISON, INC.
    Inventors: Peter Spicka, Puneet Gupta
  • Publication number: 20160333474
    Abstract: Clamping assemblies for sealing an annular chamber and reaction chamber of a reactor system are disclosed. The clamping assemblies may include actuators that are symmetrically arranged in two or more independently controllable groups of actuators.
    Type: Application
    Filed: May 12, 2015
    Publication date: November 17, 2016
    Applicant: SUNEDISON, INC.
    Inventors: Vivek Tomar, Lee William Ferry, Puneet Gupta, Satish Bhusarapu, Richard G. Schrenker