Patents Assigned to SUNEDISON
  • Patent number: 8857214
    Abstract: Methods for producing crucibles for holding molten material that contain a reduced amount of gas pockets are disclosed. The methods may involve use of molten silica that may be outgassed prior to or during formation of the crucible. Crucibles produced from such methods and ingots and wafers that are produced from crucibles with a reduced amount of gas pockets are also disclosed.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: October 14, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Steven L. Kimbel, Harold W. Korb, Richard J. Phillips, Shailendra B. Rathod
  • Patent number: 8853054
    Abstract: A method is provided for preparing multilayer semiconductor structures, such as silicon-on-insulator wafers, having reduced warp and bow. Reduced warp multilayer semiconductor structures are prepared by forming a dielectric structure on the exterior surfaces of a bonded pair of a semiconductor device substrate and a semiconductor handle substrate having an intervening dielectric layer therein. Forming a dielectric layer on the exterior surfaces of the bonded pair offsets stresses that may occur within the bulk of the semiconductor handle substrate due to thermal mismatch between the semiconductor material and the intervening dielectric layer as the structure cools from process temperatures to room temperatures.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: October 7, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Guoqiang Zhang, Jeffrey L. Libbert
  • Patent number: 8845859
    Abstract: Systems and methods are provided for mechanically cleaving a bonded wafer pair by controlling the rate of cleaving. This controlled rate of cleaving results in a reduction or elimination of non-uniform thickness variations in the cleaved surface of the resulting SOI wafer. One embodiment uses flexible chucks attached to the faces of the wafers and actuators attached to the flexible chucks to cleave the bonded wafer pair. Other embodiments also use rollers in contact with the surfaces to control the rate of cleaving.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 30, 2014
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Michael John Ries, Jeffrey L. Libbert, Dale A. Witte
  • Patent number: 8849584
    Abstract: Systems and methods are provided for determining the size of particles within a fluidized bed reactor for use with thermally decomposable silicon-containing gas. The pressure of gas adjacent a gas inlet and adjacent a gas outlet of the reactor are measured with pressure sensors. An algorithm is applied to at least one of the pressure measurements to determine the size of particles within the reactor. The determined size of the particles can be used to control the operation of the reactor.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: September 30, 2014
    Assignee: SunEdison, Inc.
    Inventors: Satish Bhusarapu, Arif Nawaz, Puneet Gupta, Karthik Balakrishnan
  • Patent number: 8846493
    Abstract: Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: September 30, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Jeffrey L. Libbert, Lu Fei, Robert W. Standley
  • Patent number: 8833564
    Abstract: A method of removing dust from granular polysilicon includes introducing a stream of granular polysilicon, dispersing the longitudinal stream of granular polysilicon by redirecting the stream into a radially outward flow having a circular pattern, and introducing a counter flow of gas in an opposite direction to that of the longitudinal stream of granular polysilicon to contact the radially outward flow to separate the dust from the granular polysilicon.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 16, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Seok-Min Yun, Seong-Su Park, Se-Myung Kim, Won-Jin Choi, Woo-Jin Yoon
  • Patent number: 8834825
    Abstract: Methods for producing silane by reacting a hydride and a halosilane are disclosed. Some embodiments involve use of a column which is not mechanically agitated and in which reactants may be introduced in a counter-current arrangement. Some embodiments involve use of a baffled column which has multiple reaction zones.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: September 16, 2014
    Assignee: SunEdison, Inc.
    Inventors: Baisheng Zou, Puneet Gupta
  • Patent number: 8828324
    Abstract: Fluidized bed reactor systems and distributors are disclosed as well as processes for producing polycrystalline silicon from a thermally decomposable silicon compound such as trichlorosilane. The processes generally involve reduction of silicon deposits on reactor walls during polycrystalline silicon production by use of a silicon tetrahalide.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: September 9, 2014
    Assignee: SunEdison, Inc.
    Inventor: Henry F. Erk
  • Patent number: 8822242
    Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: September 2, 2014
    Assignee: Sunedison Semiconductor Limited (UEN201334164H)
    Inventors: Jeffrey L. Libbert, Lu Fei
  • Patent number: 8821825
    Abstract: Methods and systems for producing silane that use electrolysis to regenerate reactive components therein are disclosed. The methods and systems may be substantially closed-loop with respect to halogen, an alkali or alkaline earth metal and/or hydrogen.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: September 2, 2014
    Assignee: SunEdison, Inc.
    Inventors: Puneet Gupta, Henry F. Erk, Alexis Grabbe
  • Patent number: 8816189
    Abstract: Integrated solar modules are provided. In one example, a corner cap for coupling to a solar module is described. The solar module has a solar panel and a frame circumscribing the solar panel. The corner cap includes a first wall and a second wall. The first wall and the second wall define a corner angle substantially the same as an angle defined by a corner of the solar module. The corner cap includes a flange extending from the corner cap. The flange is configured for coupling the corner cap to a solar module.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: August 26, 2014
    Assignee: SunEdison, LLC
    Inventors: Steven Howard Janssens, Paul J. Silberschatz
  • Patent number: 8796116
    Abstract: Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: August 5, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Alexis Grabbe, Larry Flannery
  • Publication number: 20140202525
    Abstract: A mounting bracket for use with a solar module is disclosed. The mounting bracket includes a foot including a first wall and a second wall oriented substantially orthogonal to the first wall, the first wall including serrations configured to engage serrations on a rail to adjust a height of the rail with respect to the foot. The mounting bracket further includes a backing configured to be coupled to the foot and secure the mounting bracket to the rail.
    Type: Application
    Filed: August 30, 2012
    Publication date: July 24, 2014
    Applicant: SunEdison, LLC
    Inventors: Steven Howard Janssens, Paul Joseph Silberschatz, Jesus Beltran, Daniel Freymann Koelker
  • Publication number: 20140187022
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: SUNEDISON, INC.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20140182788
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: SunEdison, Inc.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20140187023
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: SunEdison, Inc.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 8745936
    Abstract: A rack assembly is provided for mounting solar modules over an underlying body. The rack assembly may include a plurality of rail structures that are arrangeable over the underlying body to form an overall perimeter for the rack assembly. One or more retention structures may be provided with the plurality of rail structures, where each retention structure is configured to support one or more solar modules at a given height above the underlying body. At least some of the plurality of rail structures are adapted to enable individual rail structures o be sealed over the underlying body so as to constrain air flow underneath the solar modules. Additionally, at least one of (i) one or more of the rail structures, or (ii) the one or more retention structures are adjustable so as to adapt the rack assembly to accommodate solar modules of varying forms or dimensions.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: June 10, 2014
    Assignee: SunEdison, LLC
    Inventors: Joshua Reed Plaisted, Brian West
  • Publication number: 20140153303
    Abstract: A solar module device with a back plane integrated inverter device includes a substrate member having a front side and a back side. The device has a plurality of solar cells, which includes a first group of solar cells connected in a first serial configuration and a second group of solar cells connected in a second serial configuration, and a tab wire configuration formed overlying the front side of the substrate member. The tab wire includes a first interconnection coupled to the first set of solar cells in the first serial configuration and a second interconnection coupled to the second set of solar cells in the second serial configuration. The device has an inverter device coupled to a back side of the substrate member. The inverter device includes a first set of connections coupled to the first interconnection and a second set of connections coupled to the second interconnection.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: SunEdison Microinverter Products LLC
    Inventor: Suryanarayana POTHARAJU
  • Publication number: 20140141537
    Abstract: Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400° C. and about 600° C. for at least about 1 hour.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 22, 2014
    Applicant: SUNEDISON, INC.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • Patent number: 8726897
    Abstract: A collapsible rack assembly for supporting a solar module and methods of assembling the same are provided. The assembly is movable from a collapsed position to an assembled position. The assembly comprises a plurality of collapsible frames, each of which comprises a first leg, a second leg, and a third leg. The first leg extends substantially parallel to a support surface. The second leg extends from the first leg at a first angle relative to the first leg when the frame is assembled and supports the solar module at the first angle when assembled. The third leg extends from the first leg at a second angle relative to the first leg when the frame is assembled. The second and third legs are rotatably connected to the first leg. When in the collapsed position the legs are nested so that one of the legs is disposed within another of the legs.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: May 20, 2014
    Assignee: SunEdison, LLC
    Inventor: Linus Eric Wallgren