Patents Assigned to SUNEDISON
  • Publication number: 20150375495
    Abstract: Apparatus and methods for mechanically cleaving a bonded wafer structure are disclosed. The apparatus and methods involve clamps that grip the bonded wafer structure and are actuated to cause the bonded structure to cleave.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Applicant: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Gregory A. Young, Jeffrey L. Libbert
  • Publication number: 20150357180
    Abstract: Methods for cleaning semiconductor substrates with cleaning baths including ammonium hydroxide, hydrogen peroxide and a non-ionic surfactant are disclosed. The methods may result in reduced re-adhesion of released particles during cleaning which produces cleaner substrates.
    Type: Application
    Filed: June 9, 2015
    Publication date: December 10, 2015
    Applicant: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
    Inventors: Sasha Joseph Kweskin, Lara Short, Tracy M. Ragan, James R. Capstick
  • Patent number: 9209069
    Abstract: A method of preparing a high resistivity single crystal semiconductor handle wafer comprising implanting He ions through a front surface of the high resistivity single crystal semiconductor handle wafer, which is followed by an anneal sufficient to form a nanocavity layer in the damage region formed by He ion implantation. The anneal may be prior to or concurrent with thermal oxidation to prepare a front oxidized surface layer.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: December 8, 2015
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Jeffrey L. Libbert, Shilpi Vaypayee
  • Patent number: 9202711
    Abstract: A method for reducing light point defects of a semiconductor-on-insulator structure and a method for reducing the surface roughness of a semiconductor-on-insulator structure are disclosed. The methods can include a combination of thermally annealing the structure followed by a non-contact smoothing process.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: December 1, 2015
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Qingmin Liu, Jeffrey L. Libbert
  • Patent number: 9193025
    Abstract: A method of polishing a wafer is disclosed that includes determining a removal profile. The wafer is measured to determine a starting wafer profile and then the wafer is polished. The wafer is again measured after being polished to determine a polished wafer profile. The starting wafer profile and the polished wafer profile are compared to each other to determine the removal profile by computing the amount and shape of material removed from the first wafer during polishing.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 24, 2015
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Sumeet S. Bhagavat, Khiam How Low, Ichiron Yoshimura, John Allen Pitney
  • Patent number: 9188367
    Abstract: The present invention relates to a solar power generation apparatus, which comprises: torque tubes which are arranged to form a plurality of columns; a plurality of solar panels which are installed along each torque tube; posts which rotatably support each torque tube; lever arms which are coupled with each torque tube; a linkage which is disposed on the lower side of the torque tubes and is connected to each lever arm; an actuator which reciprocates the linkage in the longitudinal direction of the linkage, thereby rotating the torque tubes around an axis based on the longitudinal direction of the torque tubes; and a bed frame which is installed between some of the plurality of posts, wherein the actuator is supported thereon.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: November 17, 2015
    Assignee: SunEdison, Inc.
    Inventor: Yun-Kyu Jang
  • Patent number: 9180569
    Abstract: A platen for polishing a surface of a wafer has a reaction plate, a polishing plate, and a bladder. The reaction plate has a top and bottom surface, and defines a longitudinal axis. The polishing plate is positioned coaxially with the reaction plate. The polishing plate has a second top surface and a second bottom surface. The second top surface is adjacent to the bottom surface of the reaction plate. The bladder is coaxially located along a radially outer portion of either the top or bottom surface of the reaction plate. The bladder is connected with the polishing plate and able to expand to deform the polishing plate with respect to the bottom surface of the reaction plate.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: November 10, 2015
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Peter D. Albrecht, Sumeet S. Bhagavat
  • Patent number: 9174848
    Abstract: Processes and systems for purifying silane-containing streams and, in particular, for purifying silane-containing streams that also contain ethylene are disclosed. The processes and systems may be arranged such that one or more ethylene reactors are downstream of light-end distillation operations.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: November 3, 2015
    Assignee: SunEdison, Inc.
    Inventors: Baisheng Zou, Zhihui Gu
  • Patent number: 9170031
    Abstract: An energy transfer module coupled to a thermal solar module includes a body having a first end member, a second end member, and four side members configured to enclose a first spatial region within a vicinity of the first end member and a second spatial region within a vicinity of the second end member. The first spatial region is in communication with the second spatial region. The module further includes one or more inlet openings provided at the first end member for inputting fluid flow from the thermal solar module. The module also includes an air filter disposed within the first spatial region to remove one or more impurities from the fluid flow. Additionally, the module includes a fan disposed between the first spatial region and the second spatial region to draw the fluid flow through the air filter. The fan is coupled to a drive motor. The module further includes a heat exchanger disposed in the first spatial region and an outlet provided on the second end member.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: October 27, 2015
    Assignee: SunEdison, Inc.
    Inventors: Brian West, Charles Wade Albritton
  • Patent number: 9165802
    Abstract: Apparatus and methods for mechanically cleaving a bonded wafer structure are disclosed. The apparatus and methods involve clamps that grip the bonded wafer structure and are actuated to cause the bonded structure to cleave.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 20, 2015
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Gregory A. Young, Jeffrey L. Libbert
  • Patent number: 9159596
    Abstract: Apparatus and methods for mechanically cleaving a bonded wafer structure are disclosed. The apparatus and methods involve clamps that grip the bonded wafer structure and are actuated to cause the bonded structure to cleave.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 13, 2015
    Assignee: SunEdison Semiconductor Limited
    Inventors: Gregory A. Young, Jeffrey L. Libbert
  • Patent number: 9156705
    Abstract: Processes for producing polycrystalline silicon by thermal decomposition of dichlorosilane are disclosed. The processes generally involve thermal decomposition of dichlorosilane in a fluidized bed reactor operated at reaction conditions that result in a high rate of productivity relative to conventional production processes.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: October 13, 2015
    Assignee: SunEdison, Inc.
    Inventors: Satish Bhusarapu, Puneet Gupta, Yue Huang
  • Patent number: 9156187
    Abstract: Methods are disclosed for determining mounting locations of ingots on a wire saw machine. The methods include measuring a test surface of a test wafer previously sliced by the wire saw machine from a test ingot to calibrate the system. A magnitude and a direction of an irregularity of the measured test surface of the test wafer is then determined. The mounting location is then determined for another ingot to be mounted on the ingot holder based on at least one of the magnitude and direction of the irregularity of the measured test surface of the test wafer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 13, 2015
    Assignee: SunEdison Semiconductor Ltd.
    Inventors: Sumeet S. Bhagavat, Carlo Zavattari, Yunbiao Xin, Roland R. Vandamme
  • Patent number: 9142616
    Abstract: Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: September 22, 2015
    Assignee: SunEdison, Inc.
    Inventors: Robert J. Falster, Vladimir Voronkov
  • Patent number: 9129919
    Abstract: Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400° C. and about 600° C. for at least about 1 hour.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 8, 2015
    Assignee: SunEdison Semiconductor Limited
    Inventors: Robert J. Falster, Vladimir V. Voronkov, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • Patent number: 9114996
    Abstract: Processes for producing polycrystalline silicon by thermal decomposition of silane are disclosed. The processes generally involve thermal decomposition of silane in a fluidized bed reactor operated at reaction conditions that result in a high rate of productivity relative to conventional production processes.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 25, 2015
    Assignee: SunEdison, Inc.
    Inventors: Satish Bhusarapu, Puneet Gupta, Yue Huang
  • Patent number: 9114997
    Abstract: Processes for producing polycrystalline silicon by thermal decomposition of silane are disclosed. The processes generally involve thermal decomposition of silane in a fluidized bed reactor operated at reaction conditions that result in a high rate of productivity relative to conventional production processes.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 25, 2015
    Assignee: SunEdison, Inc.
    Inventors: Satish Bhusarapu, Puneet Gupta, Yue Huang
  • Patent number: 9117670
    Abstract: A system for depositing a layer on a substrate includes a processing chamber, a gas injecting port for introducing gas into the system, a gas distribution plate disposed between the gas injecting port and the processing chamber, the gas distribution plate including holes therein, and an inject insert liner assembly received within the system adjacent to the gas distribution plate and upstream from the processing chamber. The inject insert liner assembly defines gas flow channels therein extending along a lengthwise direction of the system, wherein each channel includes an inlet and an outlet, and at least one channel is tapered along the lengthwise direction of the system in at least one of a vertical or horizontal direction. The inject insert liner assembly has the same number of gas flow channels as the number of holes in the gas distribution plate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 25, 2015
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Arash Abedijaberi, John Allen Pitney, Shawn Thomas
  • Patent number: 9103563
    Abstract: A thermal solar system having a fire rating of at least A. In a specific embodiment, the system includes a thermal solar module having an aperture region and a backside region. The system has a shaped thickness of material having a first side and a second side. In a preferred embodiment, the shaped thickness of material is characterized by a fire rating of at least A. The material has a thickness suitable to be free from penetration of moisture according to one or more embodiments. The thickness of material also has a structural characteristic capable of maintaining a shape and coupling to the backside region of the thermal solar module according to one or more embodiments. The system also has an air plenum provided between the thermal solar module and the thickness shaped thickness of material. In a preferred embodiment, the system further has a frame assembly operably coupled to the shaped thickness of material to support the shaped thickness of material and the thermal solar module.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: August 11, 2015
    Assignee: SunEdison, Inc.
    Inventor: Eric R. Burtt
  • Patent number: 9061916
    Abstract: Processes and systems for purifying silane-containing streams and, in particular, for purifying silane-containing streams that also contain ethylene are disclosed. The processes and systems may be arranged such that one or more ethylene reactors are downstream of light-end distillation operations.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: June 23, 2015
    Assignee: SunEdison, Inc.
    Inventors: Baisheng Zou, Zhihui Gu