Abstract: A connection system for host equipment is disclosed. The system includes a plug-in electronic module and a power supply cable for plug-in connection to said module. The host equipment includes a housing for the module which effectively precludes access to the module except at one exterior end thereof. An end plate at an exterior end of the module includes a handle facilitating removal of the module from the housing. The end plate further comprises a power supply cable jack for mating with a plug of the power supply cable. The jack and the plug are so located and adapted to render ineffective the handle when the plug is mated with the jack, thereby requiring the service personnel to remove the power supply plug from the jack before removing the module from the housing.

Abstract: An entry control store in a central processing unit (CPU) is addressed by the next macroinstruction to be executed by the CPU and fetches the microcode for the first line of that macroinstruction. Subsequent lines of microcode for that macroinstruction are fetched from a main control store.

Abstract: Hardware for performing microcode branching in a pipeline central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit lines of microcode which are in the pipeline when a branch has been sensed. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupling loading and pushing to accommodate the two branching speeds. The microcode can specify loading the return address stack with a literal or register value to allow vectored branching and return to a desired line after a delayed call.

Abstract: A switching power supply uses constant current sources, switching transistors and current coupled transformers for switching current through the switching power supply. The switching current is proportional to the current of the constant current sources. The use of constant currents to drive output transistors of the switching power supply improves the efficiency of the switching power supply and desensitizes the switching power supply to variations in unregulated power sources.

Abstract: An input/output system for a processor of the kind in which a processor module has a central processing unit, a memory, an input/output channel, and a plurality of device controllers for controlling the transfer of data between the processor module and the peripheral devices includes a star poll connection in which each device controller is provided with a signalling means for signalling its identity in response to a poll operation, independently of other similarly connected device controllers such that any number of device controllers can be failed or powered off without affecting the polling of the other device controllers. The data lines in an input/output bus are used both to transmit data and to transmit signals to reduce the total number of lines needed to connect the device controllers to the channel in the star poll connection. The system is a fault tolerant system which includes an enable bit in the port of each device controller.

Abstract: A datapath system and protocol is disclosed in which data is transferred between a computer memory and one or more peripheral devices through device controllers, each of which includes a buffer, through periodic connection of the device controller to the channel. The system and protocol are structured to permit multiple device controllers to cooperatively interact on a single channel, without direct communication between device controllers. Each device controller monitors the level of stress on its buffer and at appropriate times presents a reconnect request to the channel, together with indica for permitting the channel to determine the priority of a particular request relative to other reconnect requests. The times at which a reconnect signal should be presented are determined by monitoring the level of information storage in the buffer and relating that level to a threshold level; both overfilling and overemptying are prevented.

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus.The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs.

Abstract: A multiprocessor system, the kind in which two or more separate processor modules are interconnected for two power supplies, provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional.The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function.

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller.The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time.The multiprocessor system includes a distributed power supply system which insures nonstop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system.