Abstract: A method and mechanism operate for shortening the execution time of certain macro-instructions by looking at both a present macro-instruction and a next macro-instruction. The invention includes two, interrelated aspects for accomplishing this. First, a first operation of a next macro-instruction is performed concurrently with a last operation of a current macro-instruction. Second, the next macro-instruction is decoded to determine the minimum number of clock cycles it requires. If this minimum number is below a specified number, the micro operations of the present instruction are modified to perform appropriate set-up operations for the next macro-instruction to enable it to be completed in the computed minimum number of clock cycles.

Abstract: A balanced three phase AC power supply for a computer system having unbalanced, variable DC loads. AC to DC converters utilize high power factor correction circuitry to impose a sinusoidal current loading waveshape substantially in phase with the AC voltage. Each AC to DC converter outputs equal DC voltages maintaining a balanced loading on the AC power source. The design and organization of the power supply components make the supply fault tolerant when one phase of AC power or one AC to DC converter is lost due to malfunction or servicing.

Abstract: In a data processing system, a device controller, configured to control data transfers between a processor unit and a peripheral device on an input/output bus, is provided with apparatus that permits a data transfer cycle to continue until all data has been transferred, or to allow for interruption of the data transfer cycle by another device controller requesting access to the input/output via a request signal. During a data transfer cycle the apparatus resonds to detection of the request signal to interrupt the data transfer cycle after a predetermined number of data words are transferred, permitting access to the input/output bus for other of the device controllers. In absence of the request signal, the apparatus permits the data transfer to continue until all data has been transferred between the peripheral device and the processor unit.

Abstract: An apparatus for testing cables, cable connections associated with devices and devices in a daisy chain configuration. Cable malfunctions and cable connection malfunctions can be isolated down to a single device in a daisy chain system by looping back the data bus to the control bus or vice versa. A signal is then sent out on the first bus and received back on the second bus. If a cable malfunction is present, the signal received will not be the same as the signal transmitted.

Abstract: A method and apparatus for changing the key in a cryptographic system or device are disclosed. A memory contains three storage areas for pending, active, and retired keys. New keys are loaded into the pending storage area. The key is changed by shifting the pending key into the active storage area and shifting the active key into the retired area for use by applications which have not been made aware of the key change. When an application presents a retired key, use of the retired key is allowed and the new key is returned to the application.

Abstract: A system interconnects electronic modules with one another, to a power supply and to signal lines through a printed circuit board. The modules are electrically connected to traces on the printed circuit board using blind mateable connectors. EMI shielding plates are mounted to the circuit board at the I/O connectors for the external cables. Guide elements, such as pin and socket guides and printed circuit board edge guides, are mounted to the circuit board to guide the blind mateable connectors. The syustem eliminates the numerous cables which would otherwise be required. The printed circuit board is mounted within the system housing and acts as an air duct barrier to aid proper air circulation. The circuit board also acts as a structured element helping to stabilize the housing and various module supports and serves as a mounting structure for various elements, such as cooling fans.

Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. Memory references. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references by the multiple CPUs are voted by each of the memory modules. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.

Abstract: Encoding and decoding circuits, utilizing high speed ECL-like logic, simultaneously transmit and receive multiple binary signals via a single I/O pin.

Abstract: A facsimile transmission system is used to transmit documents over telephone lines using an electronic mail system, which may be a localized system or a distributed electronic mail system. Transmission is initiated by the sending facsimile machine transmitting a mark sense cover sheet, which has a mark sense identifier printed on it, to a facsimile controller. The controller checks for the presence of the mark sense identifier and if present, the controller reads the identifying information and destination address coded thereon. The controller then transmits the identifying information and destination address and the subsequently received document facsimile data to the electronic mail system in digital form, for retransmission back through the same or a different controller to one or more receiving facsimile machines.

Abstract: The invention comprises a method for encrypting data for communication between a host computer and each of a plurality of remote terminals in a network. A method is provided for periodically generating a unique dynamic encryption key for each of said plurality of terminals using a system seed key residing only in the host computer. The dynamic encryption key generated for use by said terminal in encrypting data transmitted to said host computer and for decrypting data received from said host computer. The method includes storing at said terminal the dynamic key previously generated by said host for said terminal.

Abstract: The present invention provides an integrated circuit that has both driver and receiver functions. The circuit of the present invention has two interrelated parts. The first part of the circuit converts true TTL signals to true ECL signals. The second part of the circuit accepts true ECL signals and drives a tri-state true TTL bus. The novel design of the present invention provides a common circuit that acts as an input reference for the circuit that converts true TTL signals to true ECL signals and as a tri-state clamp for the circuit that accepts true ECL signals and drives a tri-state true TTL bus. Using the same circuit components to perform functions in two separate circuits reduces the component count of the resulting circuit and increases the circuit's power/device count figure of merit.

Abstract: An electronic module (6) and integrally mounted latch assembly (2) includes a latch handle assembly (4) mounted to the module and a keeper (8) mounted to a housing (10). The latch handle assembly includes a U-shaped handle (18) having an elongate lever (42) pivotally mounted to one leg (22) of the handle at latch end (46) of the lever. The latch end has a cam surface (64) which engages the keeper. The outer, catch end (44) of the lever is configured to engage a spring-loaded catch button (50) mounted to the other leg (20) of the handle. A disenable switch pin (72) is mounted to the handle to resiliently engage the underside (80) of the lever so that when the lever is in the latched position, the lever keeps the disenable switch pin depressed. The pin is long enough to engage an enable switch (96) within the housing when so depressed.

Abstract: A system for preserving, generating, and merging different versions of a common module that utilizes a line file storing the text of every line in a version and addressing each line with a unique line identifier. Any desired version may be generated directly without creating intermediate versions. The unique line identifiers facilitate a merge operation that does not duplicate lines.

Abstract: An insertion/extraction mechanism is used to cause blind mateable electrical connectors on an electrical module to engage and disengage mating electrical connectors in a housing by forcing the module to and from its fully inserted position within the housing. The mechanism includes a U-shaped handle pivotally mounted to the module at its ends through elastomeric sleeves. The sleeves are each mounted in a mounting hole in the module and each has a central bore within which a mounting shaft, extending from the handle, is housed. Each end of the handle has a camming surface which engages a pivot pin carried by the housing as the handle is pivoted while inserting the module into and withdrawing the module from the housing. This engagement of the camming surfaces and the pivot pins causes the handle ends and the associated mounting shafts to push radially against the elastomeric sleeves as the handle is pivoted during insertion and extraction.

Abstract: A computer program measures the execution of machine code instructions in an executing program. A copy of the measured program is made and selected machine instructions are replaced by interrupt-causing breakpoint instructions. As each breakpoint instruction is executed, the breakpoint is replaced by the actual instruction, and a bit map is updated to indicate execution of the measured instruction. Execution resumes with the actual instruction.

Abstract: A system interconnects electronic modules with one another, to a power supply and to signal lines through a printed circuit board. The modules are electrically connected to traces on the printed circuit board using blind mateable connectors. EMI shielding plates are mounted to the circuit board at the I/O connectors for the external cables. Guide elements, such as pin and socket guides and printed circuit board edge guides, are mounted to the circuit board to guide the blind mateable connectors. The system eleminates the numerous cables which would otherwise be required. The printed circuit board is mounted within the system housing and acts as an air duct barrier to aid proper air circulation. The circuit board also acts as a structured element helping to stabilize the housing and various module supports and serves as a mounting structure for various elements, such as cooling fans.

Abstract: A stack with a unary encoded stack pointer which uses the position of a single bit to point to the top of the stack. A number of multi-bit latches are used to store the data elements in the stack. A serial, bidirectional shift register is loaded with all digital zeros except for a position having a digital one (the pointer) which is coupled to the register containing the top of the stack. As new data elements are pushed onto or popped off of the top of the stack, the pointer is shifted right or left accordingly.

Abstract: A bus protocol system for interprocessor communications in valves polling the processors of a multiprocessor unit in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processor are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.

Abstract: A removable power supply interlock and extraction mechanism (2) includes a switch guard (16), mounted to the front panel (14) of a module (4), movable between a safe position when the power switch (12) is off to keep it off, and a working position, at which the switch can be freely turned on and off. When the module is being inserted into an electrical unit (16), an actuator (34), mounted to the front panel, is rotated in its insertion rotary direction (50) so the switch guard moves from its safe to its working position; simultaneously a latching element (62) on the actuator engages a latching surface (60) on the unit so to drive the module into the unit until the connectors on the module and unit are fully connected. To remove the module, the power switch is first turned off.

Abstract: Apparatus is disclosed for forming scan data path subchains from the elemental memory units of a digital system, and interconnecting the scan data path subchains to form an extended serial shift register for scan testing. The method and apparatus for forming the interconnections ensures that data is passed from one subchain to another without data being lost due to clocking irregularities.