Abstract: A storage unit for an array of modular assemblies, such as disk drives, includes a cabinet having an array of rectangular cavities open toward the front, each for receiving an assembly carrier drawer. Each carrier drawer has electrical connections for receiving an electrical assembly in the drawer. The rear of each drawer has an electrical connection panel for mating a receiving panel connected to the inside back of the cabinet, and associated with the electrical connection panels are pin-and-aperture locating and registering means for precisely aligning the carrier drawer for proper mating electrical contact with the back of the cabinet automatically as the carrier drawer is pushed fully into the cabinet. This enables disk drive maintenance to be performed quickly and efficiently by pulling out a carrier drawer and inspecting, repairing or replacing the modular assembly.

Abstract: A driver circuit for simultaneously setting up a plurality of output buffers of a 3-stage gate array into and out of a floating state using low control current. A buffer driver transistor is provided for each output buffer with the primary control path of that transistor introducing a control circuit to the respected output buffer. A common driver transistor has a primary current path which provides a control signal to the control electrodes of a plurality of buffer driver transistors. Clamp means are provided for discharging the conductor means to ground upon turn-off of the common driver transistor.

Abstract: A structural support and thin panel assembly wherein the longitudinal axis of the structural support is attached perpendicular to the thin panel comprising a structural member, a thin panel, a female member attached to the structural member and a fastening means removably attaching the female member to the thin panel.

Abstract: An electronic circuit for the generation of multiple breakpoint interrupts uses a plurality of RAMs (random access memory) wherein are stored bits such that, if all of the bit outputs of the RAM are active, then a breakpoint has been recognized. The logical combination of the RAM outputs determines the presence of a breakpoint.

Abstract: A memory system for a computer detects data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module indicating the status of operations of that memory module and is transmitted to the processor subsystem of the computer for comparison with a signal indicating the status of operations of the processor subsystem to insure that all memory modules and the memory control in the processor are receiving the same commands.

Abstract: In a multiprocessor system of the type in which two or more separate processor modules are connected by an interprocessor bus dedicated exclusively to interprocessor communication for parallel processing, there is provided an input/output system having multiported device controllers connected to the multiprocessor system by input/output buses. Each device controller is shared by pairs of the processor modules, and includes logic that ensures that only one port is selected for access at a time.

Abstract: A multiprocessor system of the kind in which two or more separate processor modules are interconnected for parallel processing includes interprocessor buses dedicated exclusively to interprocessor communication. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. An enable latch in each port dynamically disables that port from placing any signals on the related input/output bus in response to a failure of any portion of the device controller, and the enable latch is not responsive to the processor module for re-enabling the port.

Abstract: A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network is configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each successive transfer between neighboring nodes. The buffer locations are managed so that they can request an adjacent node to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.

Abstract: The disclosure relates to an input-output multiplexer demultiplexer communication channel which transfers data between a communications controller and a multiplicity of radially attached communications ports. Self-clocking serial bit-synchronous data is transferred on two opposing unidirectional data links between the communications controller and the communications channel. Serial bit-synchronous data is transferred between the communications channel and the communications ports. The communications channel uses one-bit-time response round-robin polling when the communications channel initiates transmissions from the communications ports. Data transmissions from the communications controller are multiplexed on-the-fly in the communications channel to one of the communications ports.

Abstract: A plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with any processor in another system. The network may be configured as a multi-node dual bidirectional ring having a multiprocessor system at each node. Packets of information may be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor in a selected direction between each successive transfer between neighboring nodes. The buffer locations are managed so that a node can request an adjacent node to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.

Abstract: The disclosure relates to the use of a flip flop or the like to provide additional protection against the destruction of data located in microprocessor system support circuits.

Abstract: A structural support and thin panel assembly wherein the longitudinal axis of the structural support is attached perpendicular to the thin panel comprising a structural member, a thin panel, a female member attached to the structural member and a fastening means removably attaching the female member to the thin panel.

Abstract: The present disclosure relates to a communications method for communicating data over a data channel that comprises two unidirectional communication lines. A protocol which is set of predetermined control characters is used by the communications method and the protocol is used for transferring data between communicating devices. The communications method combines acknowledgements which are control characters of the protocol transmitted in between messages, piggy-backing which is the combining of control characters of the protocol and data messages, and hold-offs with long time outs which cause the devices to enter a standby idle mode waiting for a responsive control character of the protocol. The communications system and method combines these features so as to permit improved efficient flow control of data information between the communicating devices.

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules.The multiprocessor system includes a distributed power supply system which insures non-stop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. A power interlock system and a method are provided for protection against data corruption.

Abstract: Disclosed is a base drive circuit that provides a base drive current particularly adapted to switch a switching power transistor ON and OFF quickly. The base drive current includes a variable AC impedance device that responds to a control pulse to form a base drive having (a) an initial forward base drive peak that drives the switching power transistor toward deep saturation momentarily, followed by (b) an intermediate drive current of lower magnitude, sufficient to keep a high-power transistor at or near saturation, and (c) a high-amplitude reverse drive current for high-speed turn-off of the transistor.

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored and return to a desired line after a delayed call.

Abstract: The disclosure relates to a re-vectoring circuit of a microprocessor system wherein pending interrupts are serviced without unnecessary microprocessor state store and restore operations associated with a return-from-interrupt instruction. At the conclusion of an interrupt service routine, an indirect jump instruction is executed through the same address location of an interrupt vector that the microprocessor indirectly jumped through when the microprocessor was initially interrupted. However, the indirect address is modified, that is, re-vectored to an indirect address within a predetermined address vector depending upon the type of a pending interrupt. The re-vectoring circuit recognizes the indirect jump address and then senses a pending interrupt if there is a pending interrupt. The re-vectoring circuit modifies the indirect address such that a jump occurs to the highest priority pending interrupt service routine.

Abstract: Electronic system grounding includes two system grounding paths for card caged electronic modules, with a first grounding path through the card cage and a second grounding path through the system power supply. The two system grounding paths are used to minimize noise and reduce unwanted induced superimposed transient voltage levels.

Abstract: Method and hardware associated with an arithmetic logic unit (ALU) in a central processing unit of a data processor provides for testing the inputs to the ALU to see if logical AND is zero or the two inputs are equal while allowing the ALU to perform another function at the time these tests are made.

Abstract: The present invention relates to a system for controlling multiple communications lines, so that a computer system can operate with a single component failure. Two processors are used to control two communications controllers and each of the controllers control up to 15 line controllers. Each line controller has two ports and each port is connected to a communications controller thereby providing two communications paths to each processor. Redundant power supplies are also used to provide single failure fault-tolerance. A downloadable microprocessor board is provided in combination with, but separate from, an interface board that is designed to meet various communication format specifications and the line controller comprises the two boards.