Abstract: A method, and apparatus implementing that method, for monitoring a synchronization circuit to ensure proper operation thereof. The synchronization circuit is of the type that receives asynchronously occurring input pulses to produce therefrom representations of the received input pulses, having state transitions synchronized to the state transitions of a periodic clock signal. The invention also receives the input pulses and the synchronized representation of those pulses, to ensure that for every input pulse there is provided a synchronized pulse by the synchronization circuit.

Abstract: A parity regeneration and self-check technique is used for detecting and locating errors in data communicated to, through, and from a digital subsystem. The invention utilizes a parity check associated with a data input of the subsystem, regenerating parity for data communicated from an output of the subsystem, checking the regenerated parity and comparing that check with other checks.

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and return to a desired line after a delayed call.

Abstract: A temperature alarm includes a thermostat for actuating an audible alarm, a control panel-mounted LED and a circuit board-mounted LED. The audible alarm, once actuated by the thermostat, can be temporarily disabled by the user by actuating a disable timer connected to the audible alarm. After a period of time the timer times out to return control of the audible alarm to the thermostat. The panel LED is illuminated continuously while the chosen temperature value is exceeded. The circuit board LED is mounted to a circuit board within the equipment housing. Once illuminated by the thermostat, the circuit board LED remains actuated regardless of the temperature to provide an indication to a service technician that the chosen temperature was exceeded since the last servicing. The circuit board-LED, coupled to a latching relay also mounted to the circuit board, is extinguished by manually resetting the latching relay.

Abstract: A converter for coupling a single-ended and a differential SCSI bus that facilitates the use of the ARB, SELECTION, and RESELECTION phases of the SCSI protocol.

Abstract: The present invention provdes a circuit for driving a TTL bus from an ECL circuit. The circuit of the present invention speeds up the "tri-state" to "active" transition by eliminating the need to pass the tri-state signal through a translator and buffer. A tri-state control circuit accepts true ECL input directly, thus eliminating the delay, power and density "cost" of the translator and buffer circuits. This circuit further improves the delay performance of tri-state/active transitions by restricting device saturation to low levels.

Abstract: Checking method and apparatus for monitoring the proper operation of a state machine of the type operable to produce control signals that in turn, cause other digital apparatus to produce responsive signals. Part of the checker apparatus, in effect, emulates the digital apparatus, receiving the control signals to produce therefrom emulated response signals that, when compared to the control signals, provide an indication of correct operation of the state machine means and associated circuitry.

Abstract: A cross-coupled checking circuit is disclosed in which two identical integrated circuit chips are configured in a complementary manner and connected in parallel to the same inputs and outputs. One chip drives the data output data and the other chip drives the check symbol output corresponding to the output data. Each chip generates internal results and compares them to the output driven by the other chip.

Abstract: A special-purpose, microprogrammed digital subsystem sequences through stored lists of microinstructions to produce various control signals. In response to address signals provided by an address generator, the microinstructions are accessed in pairs: A primary microinstruction and a branch or target microinstruction. For the most part, only the primary microinstruction is decoded and executed. However, certain of the ones of primary microinstructions are of the type that require a decision to be made, and the microinstruction stream branches to one of two choices depending upon the outcome of the decision. The target microinstruction forms the first microinstruction of one of the available microinstruction branches, and, if this branch is taken, is executed in parallel with the branch to avoid time penalties. An additional aspect of the invention is that the address generator, which provides address signals to a memory that stores the microinstructions, is capable of functioning as a timer circuit.

Abstract: A scan test apparatus is constructed to scan test a digital system having a memory system containing dynamic random access memory (DRAM). The scan test apparatus is given access to the memory system so that test control signals can preset the refresh counter (for the DRAM) and initialize the memory for later testing.

Abstract: Fault tolerant apparatus for generating error correcting code and, simultaneous therewith, checking the correctness of the generation, for blocks of data with which the error correcting code is associated and transmitted to a storage medium. The apparatus includes a pair of programmable control devices configured to selectively operate in one of two modes: A first mode in which data being transferred to the storage medium is monitored for generation of an error correcting code to be associated and stored with each data block, and a second mode in which the data being transferred is monitored for detecting errors that may be contained in the data. During data transmission to the storage device, one of the control devices operates in the first mode, while the other control device operates in the second mode to check operation of the first device.

Abstract: A processor system utilizing a single shared RAM array, for storing microcode and other function data, with the shared array coupled to the processor by a single shared ADR/DATA bus. In one embodiment, an onboard ROM stores selected lines of microcode and a ROM accessing system supplies microcode from the ROM when the shared RAM array is busy performing some other RAM function.

Abstract: An interleaved control store having a soft error recovery system. The system includes memory banks storing identical data sets, an error detection unit for indicating that an erroneous data element has been read from a given one of the memory banks, and a correction unit for substituting a corresponding data element read from another memory bank for the erroneous data element read from the given memory bank. Other embodiments include a feedback system for executing a branch and a dynamic, on-line memory element sparing system.

Abstract: In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs).

Abstract: A method, and apparatus to implement that method, for synchronizing an incoming signal to the transitions of a digital clock signal in the form of a periodic pulse train. The apparatus includes a first circuit pair of flip-flops arranged to sample and store the state of the input signal on either the positive and negative transitions of the periodic pulse train, an OR gate producing a signal indicative of the stored content of the first circuit, and a third circuit that samples and stores the first signal at each transition of the periodic pulse train to produce therefrom a representation of the input signal synchronized to one of the transitions of the pulse train.

Abstract: An address generation system that generates a second address relative to a first address by either incrementing, decrementing, or passing unchanged, as determined by the control digits in a LIT field, the digital number encoded by the most significant bits of the first address and substituting a selected subset of the digits in the LIT field for the least significant bits of the first address. The first address may be the program counter address and the second address the target address of a branch instruction.

Abstract: In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving the control message from a sending processor module will assume the sending processor module has failed, and operate to take over the task of the failed processor module.

Abstract: An apparatus determines the order of data communication between a plurality of peripheral devices that wish to do so and a central processor unit. Determination is made according to one of a number of selectable priority schedules. The apparatus is modifiable by programmed control so that certain of the peripheral devices can have their priorities reconfigured depending upon changing circumstances.

Abstract: The present invention provides a high speed low power electrical circuit for converting true TTL level signals to true ECL level signals. The circuit only has a single buffer delay with some small additional delay due to an input emitter follower stage. The circuit includes a clamped, switched emitter follower which acts as a level shifting comparator; a self-centering reference threshold translator; a clamped level shifted input translator; and, an ECL Buffer Driver. The circuit also includes a TTL reference and an ECL reference which are tied together. If the TTL reference level shifts slightly due to temperature changes, supply voltage shifts or other factors, the ECL voltage reference will automatically shift by an appropriate percentage to compensate for the original shift in the TTL reference.

Abstract: In a multiprocessor system comprising a plurality of individual processor modules interconnected by a bus structure, including a bus controller, for providing communication between the processor modules, a method and apparatus for interprocessor communication includes one of the processor modules sending a request signal to the bus controller to request a transmission; the bus controller polling the processor modules to identify the requesting processor module; the requestor processor module responding to the poll with the identification of the receiver processor module; the bus controller interrogating the receiver processor module to determine its status (i.e., busy or available); and the bus controller then signaling transmission commencement.