Abstract: The various functional units which comprise a central processing unit of a computer are organized so as to enable a main arithmetic logic unit and special function units including an auxilliary arithmetic logic unit to access data registers, literal constants, and data from a memory cache. A general purpose bus closely couples the functional units to the main data paths and allows the CPU sequencer to branch on numerous conditions which may be indicated via test lines. Parity from the functional units is sent to clock cycle later than results in order that the parity path does not affect machine cycle time. The architecture allows unused microcode options to be used to check for correct CPU operation by halting CPU operation on a miscompare of two buses.

Abstract: The invention is directed to a combined guide and barrier for the edge mounting of ciruit boards within a housing. The barrier guides are designed to be used in multiples in high density packing applications. The barrier guide includes a top, a bottom and a barrier extending between the top and bottom. The top and bottom have opposed grooves facing one another. The grooves guide and position the printed circuit within the housing. The barrier, positioned near and parallel to the grooves and extending along the length of the top and bottom, helps prevent the user from inadvertently coming into contact with exposed edge connectors or adjacent circuit boards after a circuit board is removed from the housing. The barrier also guides cooling air through the housing.

Abstract: An electrical keying system for a set of incompatible module pairs to prevent powerup of an electrically incompatible module pair in a set.

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ("DMA"), and a processor support module ("PSM"); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the tru-complement pair of microprocessors to operate in lockstep.

Abstract: The present invention relates to a system for controlling multiple communications lines, so that a computer system can operate with a single component failure. Two processors are used to control two communications controllers and each of the controllers control up to 15 line controllers. Each line controller has two ports and each port is connected to a communications controller thereby providing two communications paths to each processor. Two power supplies are also used to provide single failure fault-tolerance. A downloadable microprocessor is provided in combination with, but separate from, an interface board that is designed to meet various communication format specifications and the line controller comprises the two boards.

Abstract: A level sensitive scan design (LSSD) diagnostic apparatus for a data processing component. Each scan unit in a shift register chain comprises a plurality of level sensitive elements, e.g., data latches, which transfer signals from their input terminals to their output terminals in response to a "Phase B" pulse train. A multiplexer is connected to each data latch for communicating run data to the input terminal of each data latch in a normal mode of operation. In test mode, the multiplexer communicates signals from the output terminal of one data latch to the input terminal of an adjacent data latch, so that the data latch signals are serially communicated through the resulting latch chain.In order to prevent the test data from propagating uncontrollably through the serially connected latches, each multiplexer includes a test latch disposed between the test data input of the multiplexer and the output terminal of the preceding data latch in the chain.

Abstract: An apparatus for controlling the connection of an electrical module to an electrical receptacle. The module is provided with a power switch having a movable switch activator for inhibiting a flow of current to the electrical module when the switch activator is in a first position and for flowing a current to the electrical module when the switch activator is in a second position. The switch activator has a side portion which extends from a surface of the module when the switch activator is in the second position, but which does not extend from the surface of the module when the switch activator is in the first position. A lock member is disposed on a surface of the module and is slidable to a retracted position when the switch activator is in the first position. The lock member extends from the module and abuts against the side portion of the switch activator when the switch activator is in the second position.

Abstract: A fault tolerant/failsafe current limit system for shutting down a power supply if an overcurrent condition exists at one or more selected load circuits in a set of load circuits. A current limit circuit couples each selected load circuit to the power supply and includes at least two monitoring circuits for detecting whether the current delivered to the selected load circuit exceeds a preselected limit. The power supply will be shut down unless both monitor circuits agree that the delivered current does not exceed the preselected limit.

Abstract: An overlapped control store including a pair of memory elements, with each element in the pair storing a complete instruction set and with instructions from the elements accessed on alternate clock cycles. A mux, controlled by a control field in each instruction, is adapted to provide either a PC address or a target address to the control store. Unrestricted branches are facilitated because every instruction in the instruction set is included in both memory elements.

Abstract: A fault tolerant computing facility is disclosed. The facility includes a housing array for containing a plurality of hardware element modules such as disk drives, a plurality of modularized power supplies and plural power distribution modules, each being connected to a separate source of primary facility power. Each module is self aligning and blind-mateable with the housing and may be installed and removed without tools, without disturbing the electrical cabling within the cabinet, and automatically by a maintenance robot. The logical identity of each module is established by programming at a control panel and by corresponding physical location of installation of each module within the housing array.

Abstract: A system for compensating for varying attenuation of an uplink signal from a local node to a satellite. The system monitors two beacon signals and the local downlink signal to determine fade. An error signal, indicating the uplink fade, is generated and utilized to adjust the gain of the uplink transmitter to compensate for the fade.

Abstract: An improved fan, for mounting adjacent an opening in a mounting plate, includes blades rotatable about an axis and within a cylindrical housing. The fan blades move air through the opening in the mounting plate. A cylindrical, open-cell foam collar encircles the fan housing. The collar is sized so that the collar extends a substantial distance upstream past the edge of the collar. The foam collar reduces the acoustic noise from the fan by damping the housing vibration and also by acting as a barrier to muffle sound waves in the air. In addition, the foam collar straightens out the air flow prior to entering the fan blades making it more laminar and less turbulent to increase the efficiency of the fan.

Abstract: Disclosed is a method, and apparatus implementing that method, for synchronizing and managing the "system clocks" maintained by each of a number of processor units forming a multiprocessor system. Based on an averaging technique, the method includes creating a synchronization message by an originator processor unit and routing that message to other of the processor units to obtain clock values representative of each of the system clocks of each processor unit. The average clock value is then determined and that average clock value then rerouted to each of the processor units to permit them to update, if necessary, their individual system clocks to the average of all. The method further includes determining the transit times encountered by the various messages so that each processor unit can adjust the average clock value it will use to update or synchronize its system clock to account for such transit times.

Abstract: An improved EFL gate which provides concurrent true and complementary outputs. An input transistor has its base coupled to an input and its emitter coupled to an emitter of a reference transistor. The reference transistor has its base coupled to a voltage reference and its collector coupled to the base of a true output transistor. The emitter of the true output transistor provides the true output, while its collector is coupled to a voltage supply. A complementary output transistor has its base coupled to the collector of the input transistor with its emitter providing the complementary output. Its collector is coupled to the voltage supply, as is the collector of the input transistor.

Abstract: Apparatus for providing a relatively constant clocking signal to a serial input/output device from a microprocessor regardless of whether the microprocessor is executing a normal instruction cycle or an extended cycle. A state machine is driven by the same clock which drives the microprocessor and a signal from the microprocessor indicating the presence of a normal or extended instruction cycle. The state machine and the clock which drives the microprocessor drive a clocking circuit which produces a first waveform if a normal instruction cycle is being executed, and a second waveform if an extended instruction cycle is being executed. Both waveforms are edge synchronized to the clock which drives the microprocessor.

Abstract: Simplified method and apparatus for performing integrated scrambling and encoding or descrambling and decoding of block code digital transmissions is disclosed. The method involves setting the scrambling length equal to an integer multiple of the block length, and then implementing a pseudorandom number sequence generator within the block length counter. The output of the pseudorandom number sequence generator is then logically combined with the incoming data to provide scrambled data, simplifying the complexity of the encoder or decoder significantly.

Abstract: An improved method for communicating updated information among processors in a distributed data processing system. The system includes a plurality of distributed interconnected processors each having a memory. The method includes the steps of prioritizing the processors into a predetermined order, establishing one of the processors as a control processor for the broadcast of update messages, developing an update message in at least one of the processors, selecting in accordance with the control processor one of the processors which has developed an update message as a sender processor, broadcasting the update message of the sender processor to each of the processors, and causing the next processor in order to be selected as control processor in the event that the former control processor fails in service. As one preferred use, the method enables the system to transmit atomic global update messages with a tolerance to multiple processor faults.

Abstract: Apparatus is disclosed for generating pseudo-random bit patterns that are applied to a data processor, or other digital logic unit, for test purposes. In accordance with the invention, certain of the elemental storage units (e.g., flipflops) of the data processor are designed for two-mode operation: A normal mode of operation during which they operate as a part of the data processor in normal fashion, and a scan mode operation during which the elemental storage units respond to scan control signals to form a number of shift register or scan line configurations for receiving the pseudo-random sequenced or non-random sequenced test patterns generated by the apparatus. During testing, the bit patterns are passed through the scan line configurations and applied to compression circuits where, using cyclic redundancy checking (CRC), compression bit patterns received from the scan lines are achieved.

Abstract: Electronic system grounding includes two system grounding paths for card cage electronic modules, with a first grounding path through the card cage and a second grounding path through the system power supply. The two system grounding paths are used to minimize noise and reduce unwanted induced superimposed transient voltage levels.

Abstract: A digital logic circuit and method for synchronizing the leading edges skewed true-complement signal pair. The circuit is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines.