Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

Abstract: A tool (10) inserts and removes printed circuit boards (55) from a card cage (50) holding a plurality of such boards. The tool (10) has a guide (20), mounted on the card cage, a slider (30) slidably mounted to the guide, and lever arm (40), pivotally mounted to the slider. One tool can thus service all the printed circuit boards (55) in a card cage (50).

Abstract: An access control mechanism for granting, revoking, and denying authorization to computer system objects using a customer supplied set of verbs, parameters, attributes, and functions. The access control mechanism employs a processor for providing access controls to objects comprising subject memory, verb memory, object memory, definition memory, rule memory and an evaluator. The processor may be embodied as a microprocessor and memory, or a computer using software. The subject memory stores specified user attributes in a matrix having information for each user on each row, with user attributes in each field. The object memory stores object names, object attributes, and rules for defined verb names. The definition memory stores field definitions, external function declarations and strings. The rule memory stores rule names with their associated boolean expressions.

Abstract: A memory system is implemented by an array of large scale integrated dynamic random access memory elements. The memory elements are of a type that permit data way word storage on a page basis, each page being defined on a row boundary. Discovering that excess power consumption by the memory can result from successive memory operations made back-to-back to different page locations, the present invention provides counter means to count each immediately successive different page memory operations so that, when that count matches a maximum count, memory operations are stalled for a period of time.

Abstract: A bus controller, operable to grant access to a bus structure for communication between a number of individual processor modules interconnected by the bus to form a multiprocessor system, is also operable to determine the number of processors connected to the bus. The bus controller, in round-robin fashion, sequentially grants each processor access to the bus by commanding the processor to send data. The processor responds either by sending data in synchronism with a data clock supplied by the bus controller or, if no data is to be sent, responds with a no acknowledgment (NAK) signal. Initially, and periodically, the bus controller checks to determine the number of processors by, beginning with the highest identifying numbered processor, sending to that processor a send command, and looking for a response either in the form of data being sent or a NAK signal.

Abstract: A method and apparatus for synchronizing a plurality of processors. Each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit associated with the processor, the sync logic circuit generates the wait signal after the next processor event. A compare circuit associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor.

Abstract: A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU's to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU's.

Abstract: A high density electronic module packaging system includes a cabinet for housing a plurality of modules. Disposed at the rear of the cabinet and forming a rear wall thereof is a cooling system housing that is used for cooling the modules contained in the cabinet. Disposed within the cabinet are a plurality, e.g., four, cooling modules; a power distribution unit having a plurality, e.g., twelve, power converters; and a plurality, e.g., twenty-eight electronic modules. The number of cooling modules, power converters and electronic modules may be added or subtracted as needed or desired. The cooling modules flow cooling fluid to and/or from the power distribution unit and/or to the plurality of electronic modules. The power distribution unit supplies power to the plurality of electronic modules. The electronic modules may house one or more submodules such as storage devices (e.g., disk drives) or printed circuit boards.

Abstract: A high density electronic module packaging system includes a cabinet for housing a plurality of modules. Disposed at the rear of the cabinet and forming a rear wall thereof is a cooling system housing that is used for cooling the modules contained in the cabinet. Disposed within the cabinet are a plurality, e.g., four, cooling modules; a power distribution unit having a plurality, e.g., twelve, power converters; and a plurality, e.g., twenty-eight electronic modules. The number of cooling modules, power converters and electronic modules may be added or subtracted as needed or desired. The cooling modules flow cooling fluid to and/or from the power distribution unit and/or to the plurality of electronic modules. The power distribution unit supplies power to the plurality of electronic modules. The electronic modules may house one or more submodules such as storage devices (e.g., disk drives) or printed circuit boards.

Abstract: A panel is provided with a plurality of breakout elements attached to one another, and the panel, by a plurality of tab-like protrusions formed on a non-viewable surface of the panel. The breakout elements are removed by twisting the tabs for the particular element to be removed, leaving any scoring resultant from tab removal on a non-viewed surface of the panel.

Abstract: A computer system with a number of subsystems or modules on separate circuit boards employs electronic keying to ensure proper configuration of these boards. A power key arrangement associated with a plug-in connector enables a separate power supply for each set of boards. A power supply turn-on signal is routed through a uniquely-configured connector path for each board, so the power supply turn-on is inhibited for improper configurations. The uniquely-configured connector path may use either a series or a parallel implementation. The series implementation employs a set of diodes connected for conduction in either of two directions, with the mating connector having its conductor paths connected to match the diode configuration; in this manner, the power supply enable signal can only flow through the series path if the proper board is plugged into a properly-coded slot, in which case the power supply to activate this board is activated through the series path including the diodes.

Abstract: An electronic module configured to removably receive a power cord is provided with an interlock mechanism that prevents the power cord from being attached or removed while the module is in a power-on or current-drawing condition. The electronic module includes an on/off switch that, when in its on state, places the electronic module in a power-on condition. A guard mechanism is mounted to the electronic module, proximate the power switch, and is movable from a first position that captures and holds the power cord in connected condition with the electronic module, or prevents connection with the electronic module, to a second position permitting removal or connection of the power cord. Movement of the guard mechanism from the first position to the second position is permitted only if the power switch is in an off state.

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

Abstract: A method and mechanism for shortening the execution time of certain macro-instructions by looking at both a present macro-instruction and a next macro-instruction. The invention includes two, interrelated aspects for accomplishing this. First, a first operation of a next macro-instruction is performed concurrently with a last operation of a current macro-instruction. Second, the next macro-instruction is decoded to determine the minimum number of clock cycles it requires. If this minimum number is below a specified number, the micro operations of the present instruction are modified to perform appropriate set-up operations for the next macro-instruction to enable it to be completed in the computed minimum number of clock cycles.

Abstract: A queue has a plurality of serially connected transparent latches forming individual storage locations. The queue includes an entry storage latch for receiving data signals into the queue and an exit storage latch for communicating data signals out from the queue. The output terminal of each latch is connected to the input terminal of a succeeding latch so that data signals received by the entry storage latch may propagate uninterruptedly through one or more storage latches to a predetermined storage location.

Abstract: A method for processing text in a system including a host computer having a central memory unit for storing text data and a terminal unit having a local memory and a keyboard for receiving operator inputs. The host computer transfers a portion of text data to the terminal unit local memory, the terminal unit generates text editing inputs to alter the data, and the data in the local memory are altered accordingly. The terminal unit assembles audit messages which indicate a fundamental operation requested by the text editing inputs, e.g., insert text, delete text, replace text, etc., and contain the information necessary for the host computer to effect it. The audit meassages are subsequently sent to the host computer so that the host computer may alter the text in the central memory unit according to the fundamental operation indicated by the audit message.

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. Each CPU has a local memory, separate from the memory modules, and this local memory is of the dynamic type so it must be periodically refreshed.

Abstract: A system for folding the address space of a reserved segment of a high speed memory into a designated part of the address space of a cache memory included in the high speed memory. Folding information for distinguishing between cache entries that have been folded from reserved segments and those that normally map into a designated segment of the high speed memory is stored. The folding information is utilized to determine whether a cache miss occurs when the designated segment of the cache memory is accessed.