Abstract: A linear actuator system may have an actuator assembly for moving an output in translation in a first direction. A transmission has a frame, a joining link(s) pivotally connected to the frame at a first location and operatively connected to the actuator assembly at a second location for receiving movement from the output. The joining link(s) contacting an interface at a third location to cause relative movement between the frame and the interface in a second direction differing from the first direction. A motion platform system is also provided.

Abstract: A preparation method for a semiconductor structure and a semiconductor structure are provided. Herein, the preparation method comprises: providing a structure to be processed, wherein the structure to be processed comprises a substrate, and an etching target layer, a bottom mask layer and a first mask layer stacked on the substrate; patterning the first mask layer to form a first pattern, the first pattern exposing parts of the bottom mask layer; forming spacers with vertical sidewall morphology on sidewalls of the first mask layer; removing the first mask layer; filling a gap between the spacers with a filling layer, in which a material of the spacers to a material of the filling layer has a high etching selectivity ratio; and removing the spacers.

Abstract: Systems and methods that involve receiving an authentication request initiated by a relying party application on a computing device via Web Authentication (WebAuthn) interface; connecting to a nearby companion device; forwarding the authentication request to the authenticator on the companion device; receiving a response to that authentication request from the authenticator on the companion device; and transmitting the authentication response back to the sender application on the computing device for authentication purposes.

Abstract: The present application discloses a material handling system and a monitoring system and a monitoring method for particles in a traveling area of overhead hoist transfers, wherein the monitoring system for particles in the overhead hoist transfer traveling area comprises gas sampling modules, a particle counter and a monitoring device. The gas sampling module is configured to obtain the gas to be tested around traveling wheels of each overhead hoist transfer (OHT). The particle counter is configured to test the gas to be tested for the size and number of particles in the gas to be tested. The monitoring device is electrically connected to the particle counter, and is configured to acquire the size and number of the particles tested and alarm when determining that the content of particles does not meet a preset standard.

Abstract: Embodiments of the present disclosure provide an apparatus match detection method, a detection system, a prewarning method and a prewarning system, the apparatus match detection method includes: providing a to-be-detected wafer, a first detection apparatus, and a second detection apparatus; measuring by the first detection apparatus a critical dimension of the first detection area to acquire a first detection result; measuring by the second detection apparatus a critical dimension of the third detection area to acquire a third detection result; measuring by the first detection apparatus a critical dimension of the second detection area to acquire a second detection result; acquiring a measurement difference between the first detection apparatus and the second detection apparatus based on the first detection result, the second detection result, and the third detection result; and acquiring a degree of deviation between the second detection apparatus and the first detection apparatus based on the measurement di

Abstract: A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, and forming a sacrificial dielectric layer on the substrate; patterning a part of the sacrificial dielectric layer along a first direction, and forming a plurality of first trenches arranged at intervals along a second direction in the sacrificial dielectric layer; patterning a part of the sacrificial dielectric layer at bottoms of the first trenches and a part of the substrate below the part of the sacrificial dielectric layer, and forming a plurality of second trenches arranged at intervals below the first trenches, wherein the second trench has a preset depth in the substrate; forming a protective layer on sidewalls of the first trenches and sidewalls of the second trenches; and forming bit line structures in the first trenches and the second trenches.

Abstract: A semiconductor structure and a method for forming the same, and a memory and a method for forming the same are provided. The method for forming the semiconductor structure includes: providing a substrate, in which a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate; patterning the active layer and the sacrificial layer to form grooves which divide the active layer and the sacrificial layer into a plurality of active areas; filling the grooves to form a first isolation layer surrounding the active areas; patterning the active layer in the active areas to form a plurality of separate active patterns; removing the sacrificial layer via openings between adjacent active patterns to form gaps between bottoms of the active patterns and the substrate; forming bit lines in the gaps; and forming semiconductor pillars on partial tops of the active patterns.

Abstract: A refresh control circuit includes: a processing circuit, configured to receive a refresh command signal, and perform pulse combination processing on the refresh command signal to obtain a refresh combined signal, the refresh command signal having a plurality of pulses in a first time period and keeping a level state unchanged in a second time period, and the first time period and the second time period existing alternately; a logic circuit, configured to receive the refresh command signal and the refresh combined signal, and perform logical operation processing on the refresh command signal and the refresh combined signal to obtain a target control signal; and a power supply circuit, configured to receive the target control signal, and determine whether to perform a power supply operation according to the level state of the target control signal.

Abstract: An optical engine for a LiDAR system comprises an analog detection channel comprising an avalanche photodiode (APD) optically coupled to light receiving optics and bias circuitry coupled to the APD and configured to adjust a bias set point (BSP) of the APD. Sensors sense disparate environmental factors that impact optical engine performance. Memory stores pre-established APD BSP data including a nominal APD BSP and pre-established dependence data characterizing the impact of disparate environmental factors on the nominal APD BSP. A controller generates, using sensor signals, in-field dependence data characterizing the impact the disparate environmental factors currently have on the nominal APD BSP, calculate an updated APD BSP using the in-field and pre-established dependence data, and shift the BSP of the APD from the nominal APD BSP to the updated APD BSP to enhance optical engine performance.

Abstract: The invention provides an image capture device and an image processing method thereof. The image processing method includes the following steps. First, an image signal source is received by a receiving unit, wherein the image signal source has a plurality of image frames and plurality corresponding image information or plurality of corresponding variable refresh rate (VRR) related information. Next, it is determined whether the image signal source is a VRR signal, and a determination result is generated. A time stamp of each image frame is calculated according to the VRR-related information if the determination result is positive, wherein the time stamps correspond to a dynamic frame interval respectively. Next, the image frames are respectively converted into a corresponding output packet. Finally, the output packets are respectively integrated with their respective time stamps to generate a dynamic frame interval output packet.

Abstract: Infrared imaging devices are provided which are configured to implement side-scan infrared imaging for, e.g., medical applications. For example, an imaging device includes a ring-shaped detector element comprising a circular array of infrared detectors configured to detect thermal infrared radiation, and a focusing element configured to focus incident infrared radiation towards the circular array of infrared detectors. The imaging device can be an ingestible imaging device (e.g., swallowable camera) or the imaging device can be implemented as part of an endoscope device, for example.

Abstract: Embodiments of the present disclosure provide a method of manufacturing a magnetic random access memory (MRAM) and a MRAM. The method includes: preparing a bottom electrode through hole, a bottom electrode, a magnetic tunnel junction (MTJ), a top electrode, and an insulating layer sequentially on a semiconductor substrate; forming a first interlayer dielectric layer on the insulating layer; forming an etching stop layer on the first interlayer dielectric layer; forming a second interlayer dielectric layer on the etching stop layer; etching a part of the second interlayer dielectric layer above the top electrode to the etching stop layer, and forming a first trench; performing a self-alignment implantation inclined on a part of the first interlayer dielectric layer corresponding to a bottom of the first trench; continuously etching through the first trench to a top end surface of the top electrode, and forming a second trench.

Abstract: A method for detecting wafer cleaning anomalies includes: capturing a wafer cleaning video in real time through each of a plurality of cameras of cleaning machines, each camera corresponds to a respective cleaning chamber of one of the cleaning machines, and each cleaning chamber contains a nozzle; performing image processing on each frame of image contained in the wafer cleaning video to obtain characteristics of contact between a cleaning water column dispensed from the nozzle and a wafer in the image, and determining through the characteristics of contact whether the nozzle has an anomaly; and when a target nozzle having the anomaly is detected, determining anomaly positioning information of the target nozzle, and performing anomaly early-warning by using the anomaly positioning information.

Abstract: Disclosed herein are assay methods, lateral flow assay test strips, and devices for improved analyte detection. Analyte binding to target is performed both in solution phase and with a target immobilized on a surface, resulting in improved analyte detection.

Abstract: Embodiments relate to a method for fabricating a semiconductor structure. The method includes: providing a substrate, where pillars arranged in an array are formed on a surface of the substrate, and bit lines extending along a first direction are formed at bottoms of the pillars; forming, between adjacent two of the pillars, a first groove extending along a second direction; forming an isolation layer on the substrate, where the isolation layer is filled in the first groove and is filled between adjacent two of the bit lines; etching the isolation layer to expose a surface of the pillar, where a first sub isolation layer positioned in the first groove is lower than a second sub isolation layer; forming a word line surrounding a side wall of the pillar, where a surface of the word line is not higher than a surface of the second sub isolation layer; and forming a dielectric layer on the word line.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes providing a substrate having trenches, regions other than the trenches in the substrate form a plurality of active regions at intervals; forming a first isolation layer and a second isolation layer, a top surface of the first isolation layer is lower than a top surface of the second isolation layer, a groove is formed between the second isolation layer and the active region; forming a barrier layer in the groove, an etching rate of the barrier layer is lower than an etching rate of the first isolation layer; and forming a third isolation layer in an intermediate trench, the intermediate trench is filled with the third isolation layer, and the first isolation layer, the second isolation layer, the third isolation layer, and the barrier layer form an isolation structure.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a forming method of a semiconductor structure and a semiconductor structure. The forming method of a semiconductor structure includes: placing a target structure in a reaction chamber; forming a first oxide layer on the target structure, where the first oxide layer has a first thickness; and forming a second oxide layer under the first oxide layer, where the second oxide layer has a second thickness, and the first thickness is less than the second thickness.

Abstract: A semiconductor structure and a fabricating method are provided. The semiconductor structure includes a substrate, active pillars, gate structures, a metal silicide layer, and a spacer. The active pillars are positioned on the substrate and are arranged in an array, and the active pillars extend along a direction perpendicular to the substrate. The gate structures are arranged at intervals along a first direction, and the gate structures are arranged surrounding a part of the active pillars. The metal silicide layer is positioned on a top surface of the active pillar, and a projection of the metal silicide layer on the substrate is overlapped with a projection of the top surface of the active pillar on the substrate. The spacer is positioned between adjacent gate structures and adjacent active pillars, and a height of the spacer is higher than a height of a top surface of the metal silicide layer.

Abstract: A semiconductor structure includes: a plurality of transistors located in a semiconductor layer; each of the transistors including a semiconductor body extending in a first direction and a gate structure covering at least one side surface of the semiconductor body; the first direction being a thickness direction of the semiconductor layer; a plurality of conductive pillars, each of the conductive pillars being located on a top surface of a corresponding semiconductor body and being in direct contact with the corresponding semiconductor body; a memory structure covering the plurality of conductive pillars.