Patents Assigned to TECHNOLOGIES INC.
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Patent number: 12334556Abstract: A lead-based alloy containing alloying additions of bismuth, antimony, arsenic, and tin is used for the production of doped leady oxides, lead-acid battery active materials, lead-acid battery electrodes, and lead-acid batteries.Type: GrantFiled: April 15, 2024Date of Patent: June 17, 2025Assignee: RSR TECHNOLOGIES, INC.Inventors: R. David Prengaman, Timothy W. Ellis, Matthew T. Raiford
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Patent number: 12334169Abstract: A storage device updates optimal parameters associated with a Thermal Region Tag (TRT). A controller on the storage device assigns a TRT to blocks programmed at a given temperature range and updates an optimal TRT parameters by obtaining a set of representative wordlines and a set of indicative wordlines for a block assigned to the TRT. The controller performs a bit error rate (BER) estimation on indicative wordlines in the set until a valid indicative wordline is found. The controller determines whether a BER Estimation Scan (BES) check is to be performed when the valid indicative wordline is found. In performing the BES check, the controller performs the BER estimation on representative wordlines in the set until a valid representative wordline is found. When a valid representative wordline is found, the controller obtains the optimal TRT parameter and updates the optimal TRT parameter.Type: GrantFiled: October 25, 2023Date of Patent: June 17, 2025Assignee: SANDISK TECHNOLOGIES, INCInventors: Darshan Pagariya, Vishal Sharma
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Patent number: 12334771Abstract: Aspects of a storage device including a memory and a controller are provided. In certain aspects, the storage device may include a holdup circuit powered and controlled by the controller. In some examples, the holdup circuit may be configured to charge a first capacitor by closing a first switch coupled between the first capacitor and a boost converter during a first window of time. The holdup circuit may also be configured to charge a second capacitor by closing a second switch coupled between the second capacitor and the boost converter during a second window of time.Type: GrantFiled: July 7, 2023Date of Patent: June 17, 2025Assignee: SANDISK TECHNOLOGIES, INC.Inventor: Amit Vijayvargiya
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Patent number: 12336165Abstract: The disclosed semiconductor structure includes a window region, a transistor region, and a step region arranged in a first direction. The transistor region includes a word line region and a window region. The method making the semiconductor structure includes: forming active layers at intervals, forming dummy word line structures in the word line region and the step region covering the active layers at the same layer; forming a first isolation layer which a main body part and an interval part connected together, wherein the main body part is located in the window region, and the interval is located in the word line region and the step region between adjacent dummy word line structures; removing the active layers from the step region, removing the dummy word line structures; and forming a dielectric layer in the step region and the word line region. The embodiments improve the semiconductor structure's performance.Type: GrantFiled: July 20, 2022Date of Patent: June 17, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Tao Dou
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Patent number: 12336169Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure includes: providing a substrate, a plurality of spaced first trenches being formed in the substrate; forming a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer; removing the sacrificial layer with the etching holes to form air gaps; and carrying out a silicification reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches to form bit lines (BLs) in the substrate, parts of side surfaces of the BLs being exposed in the air gaps.Type: GrantFiled: May 20, 2022Date of Patent: June 17, 2025Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGYInventors: Guangsu Shao, Weiping Bai, Deyuan Xiao, Yunsong Qiu
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Patent number: 12334440Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: providing a substrate; forming an ion implantation area in the substrate, an upper surface of the ion implantation area having a distance from an upper surface of the substrate; forming an initial word line trench in the substrate, the initial word line trench extending from the upper surface of the substrate into the ion implantation area; widening the initial word line trench to form a word line trench, a width of a bottom of the word line trench being greater than a minimum width of the word line trench.Type: GrantFiled: August 15, 2022Date of Patent: June 17, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yongxiang Li, Min-Hui Chang
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Patent number: 12335230Abstract: Disclosed are various embodiments for self-service management of network address allocations using hierarchical allocation pools. A first network address pool is created for a customer of a cloud provider network. The first network address pool is divided into a second network address pool for a cloud resource of the customer. A first network address block from the second network address pool is assigned to the cloud resource.Type: GrantFiled: November 14, 2023Date of Patent: June 17, 2025Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Raunak Tibrewal, Jonathan Paul Kramer, Joseph Anthony Raccio, Eric Andrew Rubin-Smith, Shovan Kumar Das, Daniel Lawrence Iannuzzi
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Patent number: 12332625Abstract: The present application provides a method and apparatus for correcting the position of a wafer and a storage medium. The method includes: acquiring etching parameters of preset points on an etched first wafer, wherein the etching parameters include positional information and an etch rate; determining the positional information of the central point of an etch rate distribution map of the first wafer according to the etching parameters of the preset points; and correcting the position of a second wafer to be etched according to the positional information of the central point of the etch rate distribution map of the first wafer, so that the circle center of the second wafer coincides with the central point of the etch rate distribution map of the first wafer.Type: GrantFiled: September 28, 2021Date of Patent: June 17, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Zhiling Guo, Haoyu Chen
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Patent number: 12334043Abstract: A computer-implemented method of processing audio data, the method comprising receiving input audio data (x) comprising a time-series of amplitude values; transforming the input audio data (x) into an input frequency band decomposition (X1) of the input audio data (x); transforming the input frequency band decomposition (X1) into a first latent representation (Z); processing the first latent representation (Z) by a first deep neural network to obtain a second latent representation (Z{circumflex over (?)}, Z1{circumflex over (?)}); transforming the second latent representation (Z{circumflex over (?)}, Z1{circumflex over (?)}) to obtain a discrete approximation (X3{circumflex over (?)}); element-wise multiplying the discrete approximation (X3{circumflex over (?)}) and a residual feature map (R, X5{circumflex over (?)}) to obtain a modified feature map, wherein the residual feature map (R, X5{circumflex over (?)}) is derived from the input frequency band decomposition (X1); processing a pre-shaped frequency bandType: GrantFiled: May 12, 2020Date of Patent: June 17, 2025Assignee: WAVESHAPER TECHNOLOGIES INC.Inventors: Marco Antonio Martinez Ramirez, Joshua Daniel Reiss, Emmanouil Benetos
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Patent number: 12336163Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, and a semiconductor structure. The method includes: providing a substrate, where the substrate has active areas, and grooves or holes each for connecting a bit line structure to the active area are formed on a surface of the substrate; forming a protective layer, where the protective layer covers a bottom and a sidewall of each of the grooves or holes; removing the protective layer located at the bottom of each of the grooves or holes; performing pickling to remove a native oxide on a surface of each of the active areas exposed at the bottom of the grooves or holes, where partial protective layer is retained on the sidewall of each of the grooves or holes after pickling; and forming bit line structures.Type: GrantFiled: January 3, 2023Date of Patent: June 17, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Xun Yan
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Patent number: 12330293Abstract: Rotatable joints may include one or more braking assemblies. The one or more braking assemblies may control a degree of movement of the rotatable joint to provide a range of damping. In some instances, the braking assemblies may include brake band(s) that tighten and loosen around a hub, or other rotatable member of the rotatable joint. The amount of braking, or tautness of the brake band(s), may be variably controlled to arrest the hub by different amounts. In some instances, the tightening of the brake band(s) around the hub may be controlled using linear actuator(s) and/or magnetic element(s). Implementing braking assemblies having controlled actuation may improve control of rotatable joints without adding cost, complexity, weight, or bulk.Type: GrantFiled: June 29, 2020Date of Patent: June 17, 2025Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Phil Churchill, Beth A. Marcus, Hunter Sawyer
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Patent number: 12335255Abstract: Embodiments described herein provide systems and methods for secure and efficient user authentication across a variety of computing devices, such as desktops, laptops, smartphones, and tablets across operating systems such as Windows, MacOS, IOS, Android, and iPadOS. The system incorporates an authenticator application configured to communicate with internal or external user identifier scanners, such as RFID/NFC readers, fingerprint scanners, facial recognition cameras, and QR/Barcode scanners, using transport protocols like USB, BLE, or NFC. The authenticator application serves as a third-party passkey provider by interfacing with platform WebAuthn APIs, enabling WebAuthn-based authentication for native applications, browsers, and services, or alternatively as a browser extension, intercepting WebAuthn API calls directly within a browser environment.Type: GrantFiled: November 13, 2024Date of Patent: June 17, 2025Assignee: IDMELON TECHNOLOGIES INC.Inventors: Bahram Piri, Hassan Seifi
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Patent number: 12334167Abstract: A method and device for testing a memory are provided. The method includes the following operations. After activating at least one word line, at least two times of read operations are performed on a to-be-tested memory cell connected to the activated word line. Whether there is a read abnormality in the to-be-tested memory cell is determined according to an output signal obtained after the at least two times of read operations.Type: GrantFiled: July 5, 2022Date of Patent: June 17, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Dong Liu, Xikun Chu, Tianhao Diwu
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Patent number: 12336162Abstract: Embodiment relates to the field of semiconductor technology, and more particularly, to a memory, a semiconductor structure and a formation method thereof. The formation method of the present disclosure includes: providing a substrate; forming a plurality of groups of support pillars spaced apart along a first direction in the substrate, each of the plurality of groups of support pillars being spaced apart along a second direction, the first direction intersecting with the second direction; forming a support layer filling up top gaps between adjacent two of the support pillars; forming an epitaxial pillar on a top of each of the support pillars respectively by means of an epitaxial growth process; and forming a capacitor structure on a surface of a structure jointly constituted by each of the epitaxial pillars and each of the support pillars.Type: GrantFiled: June 19, 2022Date of Patent: June 17, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Guangsu Shao, Xingsong Su, Deyuan Xiao
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Patent number: 12336167Abstract: The present disclosure relates to a memory and a forming method thereof. The method of forming a memory includes: forming a stacked layer on a surface of a substrate, the stacked layer including interlayer isolation layers arranged at intervals in a first direction and a sacrificial layer group located between adjacent two of the interlayer isolation layers, the sacrificial layer group including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer sequentially stacked in the first direction, and the stacked layer including a transistor region, where the first direction is a direction perpendicular to a top surface of the substrate; removing the second sacrificial layer in the transistor region to form a first gap; and forming a gate layer and a channel layer wrapping the gate layer in the first gap.Type: GrantFiled: August 3, 2022Date of Patent: June 17, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yi Tang
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Patent number: 12336168Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a method of manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a base, and forming active layers and sacrificial layers on the base, wherein two adjacent ones of the active layers constitute an active group, there is a first distance between the active layers in the active group, there is a second distance between adjacent ones of active groups, and the first distance is greater than the second distance; forming isolation layers, wherein each isolation layer penetrates through all the active layers and all the sacrificial layers, and the isolation layers divide each of the active layers into a plurality of active structures; removing a part of the isolation layers in the word line region and a part of the sacrificial layers located in the word line region.Type: GrantFiled: September 6, 2022Date of Patent: June 17, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yi Tang
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Patent number: 12336170Abstract: Embodiments provide a method for fabricating a semiconductor structure and a structure thereof. The method includes: providing a substrate; forming, on the substrate, semiconductor channels arranged in an array along a first direction and a second direction; forming bit lines extending along the first direction, wherein the bit lines are positioned in the substrate, and each of the bit lines is electrically connected to the semiconductor channels arranged along the first direction; forming word lines extending along the second direction, wherein the word lines wrap part of side surfaces of the semiconductor channels arranged along the second direction, where one of the word lines includes two sub word lines arranged at intervals along the first direction, and the sub word lines cover part of opposite side surfaces of the semiconductor channels along the first direction; and forming isolation structures positioned between adjacent word lines and between adjacent sub word lines.Type: GrantFiled: September 25, 2022Date of Patent: June 17, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Guangsu Shao
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Patent number: 12330300Abstract: A tendon transmission system with compound tendon sheath and tendon sheath constraint element is provided. The transmission system uses the tendon, tendon sheath and ligament tissue of human hands for reference to propose a compound tendon sheath structure composed of inner tendon sheath and outer tendon sheath, which can effectively reduce the friction between tendon and tendon sheath and prevent tendon lateral shear force from damaging tendon sheath. Type I tendon sheath constraint element, type II tendon sheath constraint element, type III tendon sheath constraint element, and type IV tendon sheath constraint element are proposed. The tendon transmission system can smoothly constrain the position and motion range of the tendon sheath and prevent it from protruding abnormally, can decouple the movement of each joint across the tendon sheath from each other, and can provide a certain curling buffer space for the tendon sheath, a certain compression and impact resistance protection.Type: GrantFiled: June 2, 2022Date of Patent: June 17, 2025Assignee: NEUROCEAN TECHNOLOGIES INC.Inventor: Hualong Ren
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Patent number: 12335149Abstract: Techniques implemented by a network-access analysis system to analyze network access controls for networks, identify traffic flows that are unobserved and unrequired, and determine proposed changes to the network access controls that restrict access from unobserved traffic flows. The system may analyze the network access controls, and determine whether unrequired traffic flows are allowed to be communicated in the network. For instance, the system may analyze network flow logs and identify observed traffic flows that are required by applications in the network, and also identify unobserved traffic flows that are permitted access to, but are not observed in, the network. The system may propose changes to the network access controls to restrict network access by these unobserved traffic flows. A network administrator can receive recommendations from the system regarding the proposed changes, and determine whether they would like to implement the proposed changes to their network access controls.Type: GrantFiled: September 15, 2022Date of Patent: June 17, 2025Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Samuel Bayless, John David Backes, Vaibhav Katkade, Daniel William Dacosta, Syed Mubashir Iqbal, Nadia Labai, Patrick Trentin, Nikolaos Giannarakis, Nathan Launchbury, Divya Raghunathan
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Patent number: 12334393Abstract: The disclosed method provides a solution to the gate-induced drain leakage (GIDL) current in a semiconductor structure. The method includes forming a first trench with a first initial doped region at its bottom, oxidizing the first trench, forming a first oxide layer on the sidewalls of the first trench, and forming a second oxide layer at the bottom of the first trench. The first oxide layer's thickness is greater than the second oxide layer's thickness. The doping element of the first initial doped region prolongs the reduction rate, so that the oxidation rate of the first initial doped region is lower than the oxidation rate of the substrate, thereby forming the first oxide layer. The GIDL of the semiconductor structure can be reduced, the turn-on sensitivity of the semiconductor structure can be improved, and the yield of the semiconductor structure can be increased.Type: GrantFiled: June 30, 2022Date of Patent: June 17, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jian Yang