Patents Assigned to TECHNOLOGIES INC.
  • Patent number: 12342554
    Abstract: Embodiments provide a method for fabricating an array structure of a columnar capacitor and a semiconductor structure, relating to the field of semiconductor manufacturing technology. In the method, before a mask layer is removed, a thickness of the mask layer in the peripheral region is first adjusted to be equal to a thickness of the mask layer in the array region, thereby avoiding damage to a top support layer caused by different thicknesses of the mask layer. Moreover, in the method, a thickness of the top support layer is increased by means of a supplementary support layer, to increase support strength of the top support layer, thereby further preventing occurrence of tilt of the columnar capacitor due to insufficient support strength of the top support layer.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang Wan, Jun Xia, Kangshu Zhan, Sen Li, Tao Liu, Penghui Xu
  • Patent number: 12341025
    Abstract: Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.
    Type: Grant
    Filed: June 4, 2024
    Date of Patent: June 24, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventor: Belgacem Haba
  • Patent number: 12342575
    Abstract: The invention provides a semiconductor structure and a manufacturing method making the semiconductor structure. The method includes: providing a substrate; forming semiconductor pillars on the substrate; forming gate electrodes on the middle sidewalls of the semiconductor pillars; and performing dopant implantation to form source and drain regions. Since the gate-all-around (GAA) gates surrounding the semiconductor pillars are formed first, and the source region and the drain region are formed later by doping implantation, the precise position of the doping implantation can be ensured, thereby improving the fabrication accuracy of the semiconductor structure and improving the performance of the semiconductor structure.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qinghua Han
  • Patent number: 12342535
    Abstract: Some embodiments of the present application provide a memory forming method and a memory. The method includes: providing a substrate including at least word line structures and active regions, and bottom dielectric layers and bit line contact layers located on a top surface of the substrate, the bottom dielectric layer having bit line contact openings exposing the active regions in the substrate, and the bit line contact layers covering the bottom dielectric layers and filling the bit line contact openings; etching part of the bit line contact layers to form the bit line contact layers of different heights; forming conductive layers, top surfaces of the conductive layers being at the same height in a direction perpendicular to an extension direction of the word line structures; and the top surfaces of the conductive layers being at different heights in the extension direction of the word line structures; forming top dielectric layers.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Lingguo Zhang, Lintao Zhang, Thomas Jongwan Kwon, Xiangui Zhou, Xu Liu
  • Patent number: 12341094
    Abstract: The present disclosure provides a semiconductor structure, including: a plurality of metal layers and a substrate, wherein the plurality of metal layers include a first metal layer, a second metal layer, and a third metal layer; a plurality of virtual metal blocks and at least one signal line are disposed on the metal layers; the virtual metal blocks on the metal layers are staggered in a direction perpendicular to the substrate; a second distance between a projection of a target signal line on the substrate and a projection of a second virtual metal block on the substrate is greater than a first distance between the projection of the target signal line on the substrate and a projection of a first virtual metal block on the substrate; the target signal line is located on the first metal layer.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kun Weng
  • Patent number: 12342594
    Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding location of the source region and a corresponding location of the drain region. The gate structure includes a conductive layer having a recessed side surface facing toward the conductive plug. Compared with a traditional gate structure, in the solutions of the present disclosure, a distance between the conductive layer having the recessed side surface and the conductive plug is increased, thereby reducing a parasitic capacitance between the gate structure and the conductive plug, such that capacitances between a gate and the source/drain region are reduced, and device characteristics are improved.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tieh-Chiang Wu, Lingxin Zhu
  • Patent number: 12342525
    Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate and multiple spaced active areas on the substrate and an isolation structure between the adjacent active areas, in which, each of active areas includes multiple sub-active areas which intersect the initial bit line, and an initial bit line is provided on the substrate; patterning the active areas, the isolation structure and the initial bit line to form a word line trench located within the sub-active areas, the isolation structure, and the initial bit line, in which the remaining initial bit line serves as a bit line; forming a gate dielectric layer located on surfaces of the sub-active areas exposed by the word line trench; forming a word line and an insulating structure between the word line and the bit line, in which the word line is located on the gate dielectric layer and fills the word line trench.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jingwen Lu
  • Patent number: 12342532
    Abstract: Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate having a first surface and a second surface opposite to each other; and forming, in the substrate, active areas arranged in an array and an isolation structure configured to isolate the active areas. Each of the active areas includes a source region, a drain region, and a channel region positioned between the source region and the drain region, where the source region is exposed to the first surface. The source region includes a first region and a second region distributed in a horizontal direction, where the first region and the second region have different doping types, and the drain region and the source region are not positioned on the same surface.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Min Li
  • Patent number: 12341682
    Abstract: One example method for controlling a traffic generator using an open application programming interface (API) occurs at a vendor-agnostic traffic generator controller. The method comprises: receiving, via an open API, a vendor-agnostic test command; distributing, using at least one distribution rule, the vendor-agnostic test command to at least one service module; generating, by the at least one service module and using a translation rule, one or more device-specific commands for performing an aspect of testing or test configuration, wherein the at least one service module generates telemetry data associated with the generation of the one or more device-specific commands and the telemetry data is provided periodically or aperiodically to a data collector using an open telemetry API; and sending the one or more device-specific commands to a test related device, wherein the test related device includes a traffic generator.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: June 24, 2025
    Assignee: KEYSIGHT TECHNOLOGIES, INC.
    Inventors: Andrey John Balogh, Himanshu Ashwini, Alakendu Jana, Vibaswan Roychowdhury
  • Patent number: 12341747
    Abstract: Disclosed are various embodiments for self-service management of network address allocations in a cloud provider network. In one embodiment, a first network address pool is created for a customer of a cloud provider network in response to a first request. A second network address pool is internally reserved for the customer, where the second network address allocation is contiguous to the first network address pool. The first network address pool is expanded to include at least a portion of the second network address pool in response to a second request.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: June 24, 2025
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Jonathan Louis Pangle, Jonathan Paul Kramer, Besan Abu Radwan, Neha Mohan Tilak, Dennis So Ting Fong
  • Publication number: 20250199707
    Abstract: A storage device forms a meta block based on block erase loops. During testing of a memory device coupled to the storage device, a controller separates the physical blocks on the memory device into categories based on a check and stores block data with category markings. During use of the storage device, the controller retrieves the block data from a non-volatile memory, determines different categories from the block data, and identifies an erasure marking for a physical block. The controller forms a meta block to include the physical blocks from at least two dies. The physical blocks in the meta block have the same erasure marking. The controller also dynamically recategorizes and relinks the physical block to another meta block when a weight associated with the physical block exceeds an erase loop threshold.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 19, 2025
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: NIRANJANI RAJAGOPAL, GOPU S, RAMANATHAN MUTHIAH, RISHABH MANERKAR
  • Publication number: 20250197851
    Abstract: This invention pertains to mutant Cas9 nucleic acids and proteins for use in CRISPR/Cas endonuclease systems, and their methods of use. In particular, the invention pertains to an isolated mutant Cas9 protein, wherein the isolated mutant Cas9 protein is active in a CRISPR/Cas endonuclease system, wherein the CRISPR/Cas endonuclease system displays reduced off-target editing activity and maintained on-target editing activity relative to a wild-type CRISPR/Cas endonuclease system. The invention also includes isolated nucleic acids encoding mutant Cas9 proteins, ribonucleoprotein complexes and CRSPR/Cas endonuclease systems having mutant Cas9 proteins that display reduced off-target editing activity and maintained on-target editing activity relative to a wild-type CRISPR/Cas endonuclease system.
    Type: Application
    Filed: November 26, 2024
    Publication date: June 19, 2025
    Applicant: INTEGRATED DNA TECHNOLOGIES, INC.
    Inventors: Christopher Anthony Vakulskas, Michael Allen Collingwood, Garrett Richard Rettig, Mark Aaron Behlke
  • Publication number: 20250198029
    Abstract: Method(s) and apparatus for direct lithium extraction from brine solutions via a combined solvent extraction and electrowinning process. This process involves solvent extraction integrated with an electrodeposition of lithium metal from nonaqueous solutions to with the added feature of solvent regeneration. The direct lithium metal harvest from brines via a compatible solvent will reduce significantly operational and capital costs related to the current molten salt electrolysis methods for lithium metal production.
    Type: Application
    Filed: March 11, 2023
    Publication date: June 19, 2025
    Applicant: ENERGY EXPLORATION TECHNOLOGIES, INC.
    Inventors: Michael Z. HU, Amit PATWARDHAN, George Y. GU, David KAPLIN, Nicholas S. GRUNDISH, Sumanth CHEREDDY, Teague M. EGAN
  • Publication number: 20250199702
    Abstract: A storage device may reduce increases to a program erase cycle count associated with a physical block by forming super blocks of varying sizes. A memory device on the storage device includes one or more dies, each of which is divided into physical blocks. A controller may identify characteristics of data to be stored on the memory device. The controller may then select physical blocks from the one or more dies to be used in forming a super block and optimize the super block configuration based on data characteristics. In forming the super block with one or more physical blocks, the controller may align the super block size with the data characteristics. By aligning the super block size with the data characteristics, data relocation on the super block may be reduced and increases to the program erase cycle count associated with a physical block may be reduced.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 19, 2025
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dhanunjaya Rao Gorrle, Leeladhar Agarwal, Arvind Bhushan
  • Publication number: 20250201350
    Abstract: Methods, systems, and compositions of matter for detection, analysis and treatment of biological, chemical and radiation exposure using artificial intelligence-based systems including fuzzy logical and/or machine learning. A system capable of compiling physical, biochemical, hematological, psychological and neural datapoints, analyzing said data points and creating actionable therapeutic interventions in a graded manner based on invasiveness and probability of success. Optimized biological intervention to chemical, radiation and biochemical threats using stem cells, T regulatory cells and induced pluripotent stem cells.
    Type: Application
    Filed: December 16, 2024
    Publication date: June 19, 2025
    Applicant: CREATIVE MEDICAL TECHNOLOGIES, INC.
    Inventors: Thomas Ichim, Timothy Warbington, Amit Patel
  • Publication number: 20250195759
    Abstract: A highly integrated drug infusion device includes an infusion unit to deliver drugs; a program unit including an input end and an output end, and the input end includes a plurality of electrically connection areas for receiving the signal of analyte data, after the output end is electrically connected to the infusion unit, the program unit controls the drug delivering; an infusion cannula provided with electrodes and electrode contact point; and a conductor, one end is fixed and electrically connected to the electrode contact point, and the other end is slidably and electrically connected to the electrical connection area, when the infusion cannula is installed in the working position, the infusion cannula is connected with the infusion unit, the drug can be injected into the body through the infusion cannula, and the conductor is electrically connected to the electrical connection area, inputting signal of analyte data to the program unit.
    Type: Application
    Filed: August 3, 2022
    Publication date: June 19, 2025
    Applicant: MEDTRUM TECHNOLOGIES INC.
    Inventor: Cuijun Yang
  • Publication number: 20250198828
    Abstract: A gravimetric metering unit for bulk material has a metering means having a container for bulk material to be metered and a base unit. The base unit has a conveyor channel that feeds into an outlet line of the metering unit via a connection device having a flexible sealing element. Via the connection device, the conveyor channel can be operationally connected to the outlet line and detached again from same. The connection device has a magnetic securing arrangement for the operational connection of the sealing element at least to either the outlet line or the conveyor channel or to both.
    Type: Application
    Filed: November 14, 2022
    Publication date: June 19, 2025
    Applicant: K-TRON TECHNOLOGIES, INC.
    Inventors: Men BERNEGGER, Rolf LEHMANN, Urs HELFENSTEIN
  • Patent number: 12330000
    Abstract: A fire protection device and a fire protection method for an equipment room are provided. The fire protection device for the equipment room includes: a carbon dioxide fire extinguisher and a foam fire extinguisher; and a control module, in which the control module is configured to acquire fire information and person information, the person information representing a person situation in the equipment room, and the control module is further configured to control one of the carbon dioxide fire extinguisher or the foam fire extinguisher to extinguish fire according to the fire information and the person information, to extinguish the fire through the carbon dioxide fire extinguisher in a case that the equipment room is vacant.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: June 17, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Bangzhong Xing
  • Patent number: 12333450
    Abstract: Devices and techniques are generally described for sample size prediction for online activity. In various examples, first data related to a first sample of users interacting with an online service during a first time period may be received. In some cases, first key performance indicator (KPI) data related to the first sample of users' interaction with the online service may be received. A predicted sample size of users that will interact with the online service for a second time period following the first time period may be predicted. A predicted statistical power may be determined using the predicted sample size. In some examples, a minimum amount of time to route traffic to the online service may be determined based at least in part on the predicted statistical power.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 17, 2025
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Yu Liu, Thomas Richardson, James McQueen, Doug Hains, Will Poff, Tridiv Sardesai
  • Patent number: 12336219
    Abstract: Embodiments of the present disclosure belong to the technical field of semiconductor structure manufacturing, and specifically provide a semiconductor structure and a manufacturing method thereof. The manufacturing method specifically includes: a first gate structure on a substrate, a first conductive region and a second conductive region, wherein the first conductive region and the second conductive region are located at two sides of the first gate structure, and in a direction perpendicular to the substrate, the first conductive region and the second conductive region are located at different height positions.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: June 17, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yumeng Sun