Patents Assigned to TECHNOLOGIES INC.
  • Patent number: 12339483
    Abstract: A system for providing a conduit for light to travel between an optical fiber and a photodiode includes a tapered light coupler. A first portion of the tapered light coupler is configured to receive light from at least one optical fiber and includes a tapered region that is tapered toward a tapered end. A second portion of the tapered light coupler is coupled to and extending from the tapered end of the first portion at a junction forming an ordinary angle. The second portion includes a tapered region that is tapered toward a distal end and is configured to transfer light from the distal end to a photodiode that has a smaller surface area than a cross sectional area of the at least one optical fiber. The tapered light coupler includes a slanted surface at an exterior of the junction.
    Type: Grant
    Filed: June 21, 2024
    Date of Patent: June 24, 2025
    Assignee: KEYSIGHT TECHNOLOGIES, INC.
    Inventor: Gregory Steven Lee
  • Patent number: 12341132
    Abstract: The present disclosure provides a semiconductor structure, including a stacked structure, wherein the stacked structure includes a plurality of stacked semiconductor dies, and each of the semiconductor dies includes: a first base; a channel provided on the first base; and at least one first auxiliary through electrode and a plurality of connection through electrodes running through the first base, wherein the at least one first auxiliary through electrode is surrounded by the plurality of connection through electrodes, wherein connection through electrodes of adjacent ones of the semiconductor dies are connected through a first electrical connection structure to form a plurality of mutually isolated transmission paths, and each of the transmission paths is connected to at least one channel through at least one connection through electrode thereon.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Cheng-Jer Yang
  • Patent number: 12337541
    Abstract: Techniques for dehumidifying powder used as print material in a powder bed fusion (PBF) three-dimensional (3-D) system are disclosed. A hopper includes one or more ultrasonic transducers (UTs) positioned at strategic locations. When activated, the UTs use sound pressure at ultrasonic frequencies to agitate the powder particles held in the hopper. The movement of the particles drives moisture trapped between the particles into one or more desiccants. In various embodiments, the desiccants may be supported by desiccators suspended in the powder, such as via the casing of the hopper. In other embodiments, the desiccants may be desiccant bags provided in a desiccant insert. The moisture accumulates in the desiccants. Among other advantages, no separate thermal source is needed to dry the powder, which can be provided directly to the PBF 3-D system via the re-coater for depositing layers to form a build piece.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 24, 2025
    Assignee: DIVERGENT TECHNOLOGIES, INC.
    Inventor: Michael Thomas Kenworthy
  • Patent number: 12341397
    Abstract: A linear actuator system may have an actuator assembly for moving an output in translation in a first direction. A transmission has a frame, a joining link(s) pivotally connected to the frame at a first location and operatively connected to the actuator assembly at a second location for receiving movement from the output. The joining link(s) contacting an interface at a third location to cause relative movement between the frame and the interface in a second direction differing from the first direction. A motion platform system is also provided.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: June 24, 2025
    Assignee: D-BOX TECHNOLOGIES INC.
    Inventor: Stephan Gagnon
  • Patent number: 12342161
    Abstract: Systems and methods that involve receiving an authentication request initiated by a relying party application on a computing device via Web Authentication (WebAuthn) interface; connecting to a nearby companion device; forwarding the authentication request to the authenticator on the companion device; receiving a response to that authentication request from the authenticator on the companion device; and transmitting the authentication response back to the sender application on the computing device for authentication purposes.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: June 24, 2025
    Assignee: IDMELON TECHNOLOGIES INC.
    Inventors: Bahram Piri, Hassan Seifi
  • Patent number: 12339208
    Abstract: The present application discloses a material handling system and a monitoring system and a monitoring method for particles in a traveling area of overhead hoist transfers, wherein the monitoring system for particles in the overhead hoist transfer traveling area comprises gas sampling modules, a particle counter and a monitoring device. The gas sampling module is configured to obtain the gas to be tested around traveling wheels of each overhead hoist transfer (OHT). The particle counter is configured to test the gas to be tested for the size and number of particles in the gas to be tested. The monitoring device is electrically connected to the particle counter, and is configured to acquire the size and number of the particles tested and alarm when determining that the content of particles does not meet a preset standard.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yuanzhang Qin
  • Patent number: 12341010
    Abstract: A preparation method for a semiconductor structure and a semiconductor structure are provided. Herein, the preparation method comprises: providing a structure to be processed, wherein the structure to be processed comprises a substrate, and an etching target layer, a bottom mask layer and a first mask layer stacked on the substrate; patterning the first mask layer to form a first pattern, the first pattern exposing parts of the bottom mask layer; forming spacers with vertical sidewall morphology on sidewalls of the first mask layer; removing the first mask layer; filling a gap between the spacers with a filling layer, in which a material of the spacers to a material of the filling layer has a high etching selectivity ratio; and removing the spacers.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Longyang Chen, Shijie Bai, Zhongming Liu, Yexiao Yu, Xianguo Zhou, Bin Zhao
  • Patent number: 12341070
    Abstract: Embodiments of the present disclosure provide an apparatus match detection method, a detection system, a prewarning method and a prewarning system, the apparatus match detection method includes: providing a to-be-detected wafer, a first detection apparatus, and a second detection apparatus; measuring by the first detection apparatus a critical dimension of the first detection area to acquire a first detection result; measuring by the second detection apparatus a critical dimension of the third detection area to acquire a third detection result; measuring by the first detection apparatus a critical dimension of the second detection area to acquire a second detection result; acquiring a measurement difference between the first detection apparatus and the second detection apparatus based on the first detection result, the second detection result, and the third detection result; and acquiring a degree of deviation between the second detection apparatus and the first detection apparatus based on the measurement di
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Weigang Wang
  • Patent number: 12341125
    Abstract: A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements.
    Type: Grant
    Filed: May 22, 2024
    Date of Patent: June 24, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Guilian Gao, Laura Wills Mirkarimi, Gaius Gillman Fountain, Jr., Cyprian Emeka Uzoh
  • Patent number: 12339403
    Abstract: An optical engine for a LiDAR system comprises an analog detection channel comprising an avalanche photodiode (APD) optically coupled to light receiving optics and bias circuitry coupled to the APD and configured to adjust a bias set point (BSP) of the APD. Sensors sense disparate environmental factors that impact optical engine performance. Memory stores pre-established APD BSP data including a nominal APD BSP and pre-established dependence data characterizing the impact of disparate environmental factors on the nominal APD BSP. A controller generates, using sensor signals, in-field dependence data characterizing the impact the disparate environmental factors currently have on the nominal APD BSP, calculate an updated APD BSP using the in-field and pre-established dependence data, and shift the BSP of the APD from the nominal APD BSP to the updated APD BSP to enhance optical engine performance.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: June 24, 2025
    Assignee: LUMINAR TECHNOLOGIES, INC.
    Inventors: Adam R. Bush, Kevin A. Gomez
  • Patent number: 12340765
    Abstract: The invention provides an image capture device and an image processing method thereof. The image processing method includes the following steps. First, an image signal source is received by a receiving unit, wherein the image signal source has a plurality of image frames and plurality corresponding image information or plurality of corresponding variable refresh rate (VRR) related information. Next, it is determined whether the image signal source is a VRR signal, and a determination result is generated. A time stamp of each image frame is calculated according to the VRR-related information if the determination result is positive, wherein the time stamps correspond to a dynamic frame interval respectively. Next, the image frames are respectively converted into a corresponding output packet. Finally, the output packets are respectively integrated with their respective time stamps to generate a dynamic frame interval output packet.
    Type: Grant
    Filed: October 3, 2023
    Date of Patent: June 24, 2025
    Assignee: AVERMEDIA TECHNOLOGIES, INC.
    Inventors: Yen-Cheng Yao, Chia-Jung Hsiao
  • Patent number: 12336689
    Abstract: Infrared imaging devices are provided which are configured to implement side-scan infrared imaging for, e.g., medical applications. For example, an imaging device includes a ring-shaped detector element comprising a circular array of infrared detectors configured to detect thermal infrared radiation, and a focusing element configured to focus incident infrared radiation towards the circular array of infrared detectors. The imaging device can be an ingestible imaging device (e.g., swallowable camera) or the imaging device can be implemented as part of an endoscope device, for example.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: June 24, 2025
    Assignee: OWL PEAK TECHNOLOGIES, INC.
    Inventor: Peter N. Kaufman
  • Patent number: 12342729
    Abstract: Embodiments of the present disclosure provide a method of manufacturing a magnetic random access memory (MRAM) and a MRAM. The method includes: preparing a bottom electrode through hole, a bottom electrode, a magnetic tunnel junction (MTJ), a top electrode, and an insulating layer sequentially on a semiconductor substrate; forming a first interlayer dielectric layer on the insulating layer; forming an etching stop layer on the first interlayer dielectric layer; forming a second interlayer dielectric layer on the etching stop layer; etching a part of the second interlayer dielectric layer above the top electrode to the etching stop layer, and forming a first trench; performing a self-alignment implantation inclined on a part of the first interlayer dielectric layer corresponding to a bottom of the first trench; continuously etching through the first trench to a top end surface of the top electrode, and forming a second trench.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: June 24, 2025
    Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Xiaoguang Wang, Huihui Li, Xianqin Hu
  • Patent number: 12340833
    Abstract: A refresh control circuit includes: a processing circuit, configured to receive a refresh command signal, and perform pulse combination processing on the refresh command signal to obtain a refresh combined signal, the refresh command signal having a plurality of pulses in a first time period and keeping a level state unchanged in a second time period, and the first time period and the second time period existing alternately; a logic circuit, configured to receive the refresh command signal and the refresh combined signal, and perform logical operation processing on the refresh command signal and the refresh combined signal to obtain a target control signal; and a power supply circuit, configured to receive the target control signal, and determine whether to perform a power supply operation according to the level state of the target control signal.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Liang Zhang
  • Patent number: 12337359
    Abstract: A method for detecting wafer cleaning anomalies includes: capturing a wafer cleaning video in real time through each of a plurality of cameras of cleaning machines, each camera corresponds to a respective cleaning chamber of one of the cleaning machines, and each cleaning chamber contains a nozzle; performing image processing on each frame of image contained in the wafer cleaning video to obtain characteristics of contact between a cleaning water column dispensed from the nozzle and a wafer in the image, and determining through the characteristics of contact whether the nozzle has an anomaly; and when a target nozzle having the anomaly is detected, determining anomaly positioning information of the target nozzle, and performing anomaly early-warning by using the anomaly positioning information.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Guobiao Jiang, Xiaojun Liu
  • Patent number: 12342586
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes providing a substrate having trenches, regions other than the trenches in the substrate form a plurality of active regions at intervals; forming a first isolation layer and a second isolation layer, a top surface of the first isolation layer is lower than a top surface of the second isolation layer, a groove is formed between the second isolation layer and the active region; forming a barrier layer in the groove, an etching rate of the barrier layer is lower than an etching rate of the first isolation layer; and forming a third isolation layer in an intermediate trench, the intermediate trench is filled with the third isolation layer, and the first isolation layer, the second isolation layer, the third isolation layer, and the barrier layer form an isolation structure.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yanhong Zhang, Peng Yang
  • Patent number: 12341073
    Abstract: The present disclosure relates to the technical field of semiconductors, and provides a forming method of a semiconductor structure and a semiconductor structure. The forming method of a semiconductor structure includes: placing a target structure in a reaction chamber; forming a first oxide layer on the target structure, where the first oxide layer has a first thickness; and forming a second oxide layer under the first oxide layer, where the second oxide layer has a second thickness, and the first thickness is less than the second thickness.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Huiwen Tang
  • Patent number: 12341025
    Abstract: Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.
    Type: Grant
    Filed: June 4, 2024
    Date of Patent: June 24, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventor: Belgacem Haba
  • Patent number: 12342575
    Abstract: The invention provides a semiconductor structure and a manufacturing method making the semiconductor structure. The method includes: providing a substrate; forming semiconductor pillars on the substrate; forming gate electrodes on the middle sidewalls of the semiconductor pillars; and performing dopant implantation to form source and drain regions. Since the gate-all-around (GAA) gates surrounding the semiconductor pillars are formed first, and the source region and the drain region are formed later by doping implantation, the precise position of the doping implantation can be ensured, thereby improving the fabrication accuracy of the semiconductor structure and improving the performance of the semiconductor structure.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qinghua Han
  • Patent number: 12341094
    Abstract: The present disclosure provides a semiconductor structure, including: a plurality of metal layers and a substrate, wherein the plurality of metal layers include a first metal layer, a second metal layer, and a third metal layer; a plurality of virtual metal blocks and at least one signal line are disposed on the metal layers; the virtual metal blocks on the metal layers are staggered in a direction perpendicular to the substrate; a second distance between a projection of a target signal line on the substrate and a projection of a second virtual metal block on the substrate is greater than a first distance between the projection of the target signal line on the substrate and a projection of a first virtual metal block on the substrate; the target signal line is located on the first metal layer.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kun Weng