Abstract: Integrated vehicle structures are provided herein. An integrated vehicle structure can include an enclosure portion configured to house an electric motor and a plurality of extended portions extending from the enclosure portion. The enclosure portion and the plurality of extended portions can be load-bearing and configured to bear vehicle loads. The extended portions of the integrated vehicle structures can include a connection portion configured to connect with another load-bearing structure to at least receive or transmit loads. The plurality of extended portions can be configured to transfer vehicle loads along physically separate paths. A portion of the enclosure portion can define an opening configured to allow a drive shaft to connect the electric motor to a wheel. The enclosure portion can be configured with an opening for allowing the installation and removal of the electric motor.

Abstract: Embodiments of the present disclosure disclose a lithography method, a lithography apparatus, and a computer storage medium. The method includes: determining an exposure intensity of a mask aligner; determining a target preset interval corresponding to the mask aligner according to the exposure intensity; determining, according to the target preset interval, at least one target wafer for which at least one exposure dose is a target exposure dose, the target preset interval has a corresponding relationship with the target exposure dose; and performing lithography process on the at least one target wafer by using the mask aligner.

Abstract: A pixel array includes pixel circuits including a first pixel circuit having a first split floating diffusion receiving charge from first and third photodiodes through first and third transfer transistors, and a second split floating diffusion receiving the charge from second and fourth photodiodes through second and fourth transfer transistors. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits.

Abstract: A method for determining bone mass density (BMD) of a patient includes obtaining X-ray scan data of a region of interest (ROI) of the patient using an energy discriminating photon counting radiation detector, and calculating the bone mass density (BMD) of the region of interest of the patient based on detected X-ray photon counts within three or more energy bins.

Abstract: This disclosure describes techniques for providing instructions when receiving biometric data associated with a user. For instance, an electronic device may detect a portion of a user, such as a hand. The electronic device may then determine locations of the portion of the user relative to the electronic device. Based on the locations, the electronic device may cause a visual indicator to provide instructions to the user for placing the portion of the user at a target location relative to the electronic device. For example, the visual indicator may emit light indicating that the portion of the user is off-centered, angled, too low, and/or too high. After providing the instructions and determining that the portion of the user is at the target location, the electronic device may capture at least an image of the portion of the user and use the image to identify an account.

Abstract: Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a substrate, the substrate being provided with a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction, and a depth of each of the plurality of first trenches being less than a depth of each of the plurality of second trenches; forming a first isolation structure to cover the substrate and fill the plurality of first trenches and the plurality of second trenches; forming a plurality of third trenches positioned in the substrate at bottoms of the plurality of first trenches and extending along the first direction; forming a second isolation structure to fill the plurality of first trenches and the plurality of third trenches; forming gate structures surrounding the substrate between the plurality of first trenches along the second direction.

Abstract: An apparatus and method are provided for a night vision system including a transparent overlay display that transmit direct-view light representing an intensified image and emits display light representing a display image. The transparent overlay display is a borderless display in which the active area extends to at least one edge of the display. Data-handling circuitry is arranged within the active area, rather than being arranged along a border of the display. The data-handling circuitry may be fabricated in the active area of the display by fabricating it below opaque pixel regions that generate the display light. This borderless configuration allows partial overlap with the intensified image by eliminating opaque borders in which the data-handling circuitry is fabricated. This borderless configuration helps to minimize size, weight, and power by reducing the size of the display and eliminating the need for bulky beam splitters.

Abstract: A chip package structure and a storage system are provided. The chip package structure includes a chipset, a first Re-Distribution Layer (RDL), and a bonding pad region. The chipset includes a plurality of chips distributed horizontally. The first RDL is disposed on a first surface of the chipset. The bonding pad region includes a plurality of bonding pads, the plurality of bonding pads are located on a side surface of the first RDL away from the chipset, and the plurality of bonding pads are connected to the plurality of chips through the first RDL.

Abstract: A control apparatus includes: a receiving circuit, configured to receive a read clock signal from the memory, and output the read clock signal; a clock circuit, configured to generate a first internal clock signal; a selection circuit, configured to receive the read clock signal and the first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal; and a latch circuit, configured to receive the target read clock signal and a read data signal sent by the memory, and perform latch processing on the read data signal by using the target read clock signal.

Abstract: A smoke evacuation flow regulator for use with a suction source to rapidly remove excess smoke during an endoscopic surgical procedure is described. The smoke evacuation regulator may include a body having a gas pathway and a knob assembly threadably attached to the body that is sized to completely open or completely close the gas pathway in a single revolution of the knob assembly. The head of the knob assembly may be sized and shaped to permit tactile determination of the rotational position of the knob assembly in low vision situations. The body of the smoke evacuation flow regulator may include a knob assembly retaining arm that cooperates with a disk or extension on the knob assembly to allow rotational freedom of the knob assembly, but prevent inadvertent removal of the knob assembly from the body during use.

Abstract: A pop-up sensor head with a camera transitions between a retracted and extended state. While retracted, the camera lens is covered. While extended, the camera lens is exposed and available for use. A motor maintains the sensor head at a setpoint position, such as in the retracted or extended state. A position data, such as from a Hall effect sensor associated with the motor, may be used to determine a displacement of the sensor head due to an external force being applied, such as a user pressing on the sensor head. Responsive to this input, the sensor head may transition between the retracted and extended state.

Abstract: Pixel designs with reduced LOFIC reset and settling times are disclosed herein. In one embodiment, a pixel cell includes a photosensor configured to photogenerate image charge in response to incident light, a floating diffusion to receive the image charge from the photosensor, a transfer transistor coupled between the floating diffusion and the photosensor to transfer the image charge to the floating diffusion, and a first reset transistor coupled between the floating diffusion and the voltage supply. The pixel cell further includes a capacitor having two ends, and a second reset transistor. A first end of the capacitor is coupled to the floating diffusion. The second reset transistor is coupled between a second end of the capacitor and the voltage supply.

Abstract: Aspects of the present disclosure relate generally to night-vision systems and more specifically to an integrated flex circuit. One example illustrated herein includes a method of upgrading a night-vision system. The method may include attaching a flex circuit to an intensifier module, in which the flex circuit includes one or more light detectors. The method may include inserting the intensifier module into a housing and folding the flex circuit to expose the one or more light detectors.

Abstract: Systems, apparatuses, semiconductor products and methods for semiconductor packages, specifically under chip bridge system-in-packages, are provided that allow one or more bridges to connect two or more dies. For example, high density connections of two or more dies may be connected with an under chip bridge, all of which may be placed on a substrate to form a system-in-package semiconductor package. Various embodiments include methods of manufacturing such packages that include utilizing a flat semiconductor along with bumping operations that may use single sizes of bumping.

Abstract: The instant invention describes an anti-biofouling structure for placement onto structures or surfaces that are exposed to aquatic environments. Embedded within the anti-biofouling structure are agents that can diffuse out of the structure and prevent the formation and/or accumulation of plant and animal species build-up that creates biofouling. The instant invention also describes a system for preventing biofouling of an object stored in an aquatic environment which includes the anti-biofouling structure, and a protective cover element constructed and arranged to fit various structures, such as boat propellers.

Abstract: A memory and a method for preparing a memory are provided. The method for preparing the memory includes: providing a substrate, in which the substrate includes a first N-type active region and a first P-type active region; forming an epitaxial layer covering the first P-type active region, in which the epitaxial layer exposes the first N-type active region; simultaneously forming a first gate dielectric layer covering the first N-type active region and a second gate dielectric layer covering the epitaxial layer, in which a thickness of the first gate dielectric layer is substantially the same as a thickness of the second gate dielectric layer; forming a first gate covering the first gate dielectric layer to form a first N-channel Metal Oxide Semiconductor (NMOS) device; and forming a second gate covering the second gate dielectric layer to form a first P-channel Metal Oxide Semiconductor (PMOS) device.

Abstract: The present disclosure provides a memory device and a ZQ calibration method. The memory device includes a master chip and a plurality of slave chips. The master chip and the slave chips are each provided with a first transmission terminal and a second transmission terminal, where the first transmission terminals are connected to each other, and the second transmission terminals are connected to each other; and a first signal receiver and an address transmitter are provided in the master chip, and a second signal receiver is provided in the slave chip, the address transmitter is configured to send an address signal; a current slave chip sends the ZQ flag signal after completing the calibration; and the address transmitter is configured to send a next address signal.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes coupled to bit lines. A control means successively applies each of a series of pulses of a program voltage to selected ones of the word lines while simultaneously applying one of a bit line program voltage and a bit line inhibit voltage to ones of the bit lines coupled to the memory holes containing groups of the memory cells connected to the selected ones of the plurality of word lines to program the groups of the memory cells with data. The control means maintains a voltage applied to ones of the plurality of bit lines as the bit line inhibit voltage in response to the ones of the plurality of bit lines remaining unselected when programming a next one of the groups of the memory cells.

Abstract: A memory device and a manufacturing method therefor. A film-stack structure is formed on a substrate, the film-stack structure includes sacrificial layers and active layers alternately stacked in a first direction. Part of the film-stack structure located in a first area is removed. A plurality of first grooves spaced apart from each other and extend in a second direction are formed, where the substrate is exposed from the first grooves to divide the active layers located in the first area into a plurality of active pillars spaced apart from each other. The sacrificial layers located in the first and second areas are removed. Part of the active layers located in the second area is removed, to form a plurality of step-shaped connection layers on an end of the second area away from the first area. Gate material layers are formed to cover the connection layers and the active pillars.

Abstract: Embodiments disclose a buried bit line structure, a method for fabricating the buried bit line structure, and a memory. The buried bit line structure includes: a substrate having a bit line trench; a bit line metal filled in the bit line trench; and a bit line contact filled in the bit line trench and positioned on the bit line metal, where an arc-shaped contact surface is provided between the bit line contact and the bit line metal. By setting a contact surface between the bit line contact and the bit line metal to be the arc-shaped contact surface, a contact area between the bit line contact and the bit line metal is increased, electrical conductivity of the bit line structure is enhanced.