Abstract: A temperature control device and a temperature control method are provided. The temperature control device is located at an interface between a photoresist coating and developing machine and a lithography machine and includes: a temperature detection device, a gas flow generator and a controller. The temperature detection device and the gas flow generator are respectively connected to the controller. The temperature detection device is configured to detect an actual temperature at the interface in real time. The gas flow generator is at least configured to generate a gas flow sealing knife around the interface. The controller is configured to control the gas flow generator to generate the gas flow sealing knife responsive to that the actual temperature detected by the temperature detection device is not equal to the target temperature, to control the actual temperature at the interface to reach the target temperature through the gas flow sealing knife.

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a metal barrier layer, and a solder layer. The metal pad is arranged on the semiconductor substrate; the bump is arranged on the metal pad; the metal barrier layer is arranged on the side of the bump away from the metal pad; the metal barrier layer contains a storage cavity; the sidewall of the metal barrier layer is configured with an opening connecting to the storage cavity; the solder layer is arranged inside the storage cavity, and the top side of the solder layer protrudes from the upper side of storage cavity. During the flip-chip soldering process, solder is heated to overflow, the opening allows the solder flow out through the opening. The openings achieve good solder diversion in overflow, thus mitigating the problem of solder bridging between bumps.

Abstract: A device for delivery of a therapeutic agent to a surgical cavity, including: a porous, mucoadhesive, freeze-dried polymeric matrix having first and second opposed surfaces, the matrix formed by a composition including chitosan; a plurality of particles embedded within the matrix, the particles containing the therapeutic agent and having a coating around the therapeutic agent, the coating including chitosan. The first surface of the matrix is configured to be applied to the surgical cavity; the device releases the particles through the first surface; the device is also sterilized and provides release of approximately 20% to 100% of the therapeutic agent within 20 minutes of application to the surgical cavity.

Abstract: Motorized cartridges and coordinate measuring machines having motorized cartridges are provided. The motorized cartridges include a cartridge housing having a shaft passing therethrough, a measurement probe coupled to shaft and arranged to detect movement of the shaft, and an integrated motor operably coupled to the shaft and arranged to drive movement of the shaft.

Abstract: A network information transmission method, comprising the following steps: receiving a first media information by a first terminal device; processing the first media information to obtain a processed first media information; integrating the processed first media information into a second media information to generate an integrated second media information; outputting the integrated second media information to a second terminal device through the network; decompressing the integrated second media information through the second terminal device; capturing the integrated second media information through the second terminal device; obtaining the first media information based on the integrated second media information; and playing the first media information by the second terminal device.

Abstract: Disclosed are methods, devices, and computer-readable media for detecting lanes and objects in image frames of a monocular camera. In one embodiment, a method is disclosed comprising receiving a plurality of images; identifying a horizon in the plurality of images by inputting the plurality of images into a deep learning (DL) model (either stored on a local device or via a network call); determining one or more camera parameters based on the horizon; and storing or using the camera parameters to initialize a camera.

Abstract: Methods, systems, and computer readable media for conducting a network traffic simulation using hypertext transfer protocol (HTTP) archive (HAR) data are disclosed. One method includes receiving HAR file information generated by a web client entity in a test environment, utilizing at least a portion of the HAR file information to generate one or more HTTP transaction test definitions, and utilizing the one or more HTTP transaction test definitions to generate an associated web application server emulation used for performing a test on a system under test (SUT). The method further includes utilizing the web application server emulation to generate a plurality of test packets and generating associated performance metric data representative of the SUT in response to the SUT processing the plurality of test packets.

Abstract: A real-time spectrum analyzer (RTSA) includes an analog-to-digital converter (ADC) configured to convert in real-time an input analog signal into a digital input data stream, a digital down-converter (DDC) configured to down-convert in real-time the digital input data stream into a down-converted input data stream, a fast Fourier transform (FFT) unit configured to generate in real-time FFTs of the down-converted input data stream, an acquisition memory circuit configured to store in real-time the FFTs generated by the FFT unit, and an analyzer configured to read in non-real time the FFTs stored in the acquisition memory.

Abstract: The present application provides a memory and a memory fabricating method. The memory includes a substrate, on which is disposed a separation layer, in which are arranged plural bitlines spaced apart from one another, the plural bitlines are arranged along a first direction, and each bitline is S-shaped. The method of fabricating the memory comprises the following steps: providing a substrate; forming on the substrate plural bitline grooves; forming in each bitline groove a first separation layer; forming bitlines on the first separation layer; forming a second separation layer on the bitlines; removing the substrate between adjacent separation walls, the separation wall including the first separation layer, the bitlines, and the second separation layer; and forming a third separation layer in a space between the adjacent separation walls, the third separation layer, the second separation layer, and the first separation layer together forming a separation layer.

Abstract: A semiconductor package assembly and manufacturing method are provided. The assembly includes: a base plate having a first surface; a chip stacking structure located on the base plate, the chip stacking structure including multiple chips sequently stacked in a direction perpendicular to the base plate and being electrically connected to the first surface; an interposer located on the chip stacking structure and having a first interconnection surface, the first interconnection surface having first and second interconnection regions, and the first interconnection region being electrically connected to the base plate; and a molding compound sealing the chip stacking structure, interposer and first surface. The first interconnection region is not sealed by the molding compound and the second interconnection region is sealed by the compound. There is a preset height between a top surface of the molding compound on the second interconnection region and the first interconnection region.

Abstract: A control apparatus includes: a receiving circuit, configured to receive a read clock signal from the memory, and output the read clock signal; a clock circuit, configured to generate a first internal clock signal; a selection circuit, configured to receive the read clock signal and the first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal; and a latch circuit, configured to receive the target read clock signal and a read data signal sent by the memory, and perform latch processing on the read data signal by using the target read clock signal.

Abstract: A semiconductor package structure includes: a first base plate provided with a first surface; a first chip stack body located on the first base plate, where the first chip stack body includes a plurality of first semiconductor chips successively stacked onto one another in a direction perpendicular to the first base plate, and is electrically connected to the first surface of the first base plate; an interposer layer located on the chip stack body and provided with a first interconnection surface, where the first interconnection surface is provided with a first interconnection region electrically connected to the first base plate and a second interconnection region; and a molding layer configured to seal the first chip stack body, the interposer layer and the first surface of the first base plate. The first interconnection region is unsealed by the molding layer, and the second interconnection region is sealed by the molding layer.

Abstract: A memory includes a substrate; a plurality of bit lines on the substrate, which are parallel to each other and extend in a first direction; a plurality of active pillars on the bit lines, bottom ends of which are connected to the bit lines; a plurality of word lines parallel to each other and extending in a second direction, which surround outer sidewalls of the active pillars, and expose top ends of the active pillars, the active pillars and the word lines jointly constitute vertical memory transistors of the memory; and a plurality of capacitors and a plurality of connecting pads, each of the capacitors is located on each of the active pillars, each of the connecting pads is located between the active pillar and the capacitor.

Abstract: A semiconductor package structure includes a first package structure and a second package structure. The first package structure includes a chip stacking structure and a molding compound. A first conductive block is disposed on the chip stacking structure. The molding compound wraps the chip stacking structure and exposes the first conductive block. The second package structure is disposed on the chip stacking structure and electrically connected to the first conductive block. A gap is formed between the first package structure and the second package structure.

Abstract: A driving structure of a drug infusion device, includes at least one driving unit and at least one driving wheel; a linear actuator connected with the driving unit; a switch unit electrically connected with the linear actuator; a power supply, the power supply, the switch unit and the linear actuator electrically connected to form a power supply circuit; and a program unit, including a timer electrically connected to the switch unit, when the timer works, the switch unit is closed to turn on the power supply circuit, and the linear actuator is powered; when the timer stops working, the switch unit is opened to disconnect the power supply circuit, and the linear actuator stops being powered, which makes the infusion device have multiple different infusion modes and improves user experience.

Abstract: Methods, systems, devices, processes and others for geo-fence service discovery including a device with a geo-fence detection engine and a services detection engine; wherein the geo-fence detection engine identifies the device entering a geo-fenced location; and wherein the services detection engine administers services through requests and responses between the services detection engine of the device and the services administration module administering the geo-fenced location services provided while the device is withing the geo-fenced location.

Abstract: Various embodiments disclosed relate to methods of predicting neutral detergent fiber digestibility (NDFD) properties of a feedstuff sample. A method of predicting neutral detergent fiber digestibility (NDFD) properties of a feedstuff sample includes collecting a near-infrared spectrum of the feedstuff sample to provide NIR data of the feedstuff sample. The method also includes predicting NDFD of the sample at an elapsed time, NDFD rate of the sample, and/or NDFD extent of the sample from the NIR data using a NIR/NDFD calibration model. Various embodiments provide a method of developing the NIR/NDFD calibration model using in vitro gas production (IVGP). Various embodiments provide a method of predicting digestibility of the feedstuff sample for an animal at a rumen passage rate (eNDF).

Abstract: A bilaterally driven drug infusion system, includes: an infusion unit, including a drug storage unit; a piston and a driving wheel respectively connected with a screw, the driving wheel, provided with wheel teeth, driving the screw movement by rotation, the piston arranged in the drug storage unit, the screw advancing the piston to move; a driving unit, cooperated with the driving wheel; a power unit, connected to the driving unit; a control unit, controlling the driving unit to output forces in two different directions on the driving unit; and sensing unit, operatively connected to the control unit and used to sense or recognize the user's body movements, and different body movements represent different functional instructions, and according to the body movement sensed or recognized by the sensing unit, the control unit controlling the infusion unit to execute corresponding functional instructions.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: forming an active region on a substrate; forming at least one trench in the active region, the trench at least dividing the active region into a source region on one side of the trench and a drain region on the other side of the trench; and forming an elevated source region and an elevated drain region on the source region and the drain region respectively.

Abstract: Disclosed are a method of underlying drive forwarding and a multi-core system implemented based on a UEFI, which can increase a running speed of the multi-core system implemented based on a UEFI. The underlying drive forwarding method is configured for underlying drive forwarding of a multi-core system. The multi-core system is implemented based on a UEFI and includes an application processor and a bootstrap processor. The bootstrap processor is provided with an execution interface configured to call underlying hardware. The application processor is configured with an instruction interface corresponding to the execution interface.