Abstract: A method for forming a storage node contact structure and semiconductor structure are provided. The method includes providing a substrate having a surface on which bit line structures are formed; forming a groove at a part, corresponding to an active region, of bottom of the contact hole; and growing a silicon crystal from the groove in the contact hole by using an epitaxial growth process, and controlling growth rates of the silicon crystal in a first and second directions in a growth process to enable the growth rate of the silicon crystal in the first direction to be greater than the growth rate of the silicon crystal in the second direction at beginning of growth and enable the growth rate of the silicon crystal in the first direction to be equal to the growth rate of the silicon crystal in the second direction at end of the growth.

Abstract: An optical device includes an underlying device configured to output light in a first spectrum. A stacked device is coupled to the underlying device and configured to be coupled in overlapping fashion to an optical output of the underlying device. The stacked device is transparent to light in the first spectrum. The stacked device includes electro-optical circuits including: light emitters and detectors. Each detector is associated with one or more light emitters. Each detector is configured to detect light emitted from the underlying device. The light emitters are configured to output light dependent on light detected by an associated detector. Optical filters are optically coupled to an optical input of the underlying device. Each filter is aligned with a detector to suppress absorption of certain wavelengths of light by the underlying device thereby affecting light detected by the detectors and thus further affecting the light output by the light emitters.

Abstract: Example embodiments involve a metrics collection system for collecting software usage metrics from one or more client devices at deployments. A computer, such as a server configured to execute the metrics collection system, collects software usage metrics (e.g., as a metrics submission from a client device) of the software product at the deployment, identifies a metrics type of the software usage metrics collected, assigns the software usage metrics to a metrics category, and calculates and updates a metrics score of the metrics category, based on the software usage metrics collected.

Abstract: The present disclosure provides a memory device test method, apparatus, and system, a medium, and an electronic device. The memory device test method includes: determining an operation path according to position coordinates of a target test platform and current position coordinates of a memory device; setting a movable apparatus according to the operation path, such that the movable apparatus moves the memory device into the target test platform according to the operation path; controlling the target test platform to test the memory device according to a target test program; and monitoring a test result of the memory device in real time, and storing the test result of the memory device into a database.

Abstract: A neural network is trained to process input data and generate a classification value that characterizes the input with respect to an ordered continuum of classes. For example, the input data may comprise an image and the classification value may be indicative of a quality of the image. The ordered continuum of classes may represent classes of quality of the image ranging from “worst”, “bad”, “normal”, “good”, to “best”. During training, loss values are determined using an ordered classification loss function. The ordered classification loss function maintains monotonicity in the loss values that corresponds to placement in the continuum. For example, the classification value for a “bad” image will be less than the classification value indicative of a “best” image. The classification value may be used for subsequent processing. For example, biometric input data may be required to have a minimum classification value for further processing.

Abstract: The application provides a method for manufacturing a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors. The method for manufacturing the semiconductor structure includes: providing a base; sequentially stacking an initial conductive layer, an initial first dielectric layer, an initial first mask layer, an initial second dielectric layer, an initial second mask layer and a photoresist layer with a pattern on the base; and etching part of the initial second mask layer, part of the initial second dielectric layer and part of the initial first mask layer by taking the photoresist layer as a mask, so as to form a second dielectric layer with a trapezoidal structure which is of a structure with small top and large bottom.

Abstract: A method for forming a semiconductor structure and a semiconductor structure are provided. The method includes: a stacked structure is formed on a surface of a substrate, the stacked structure including supporting layers and sacrificial layers which are alternately stacked; a buffer layer is formed on a surface of the stacked structure facing away from the substrate; capacitor holes penetrating through the stacked structure and the buffer layer and exposing capacitor contacts are formed; a first electrode layer covering inner walls of the capacitor holes is formed; an etching window penetrating through the buffer layer is formed; part of the supporting layers and all of the sacrificial layers in the stacked structure are removed along the etching window; the buffer layer is removed; and a dielectric layer and a second electrode layer are formed to form a capacitor.

Abstract: A refresh counter circuit, a refresh counting method and a semiconductor memory are provided. The refresh counter circuit includes: a first signal generator that is configured to generate a first carry signal according to each of refresh pulse signals generated by a received refresh command; a second signal generator that is configured to generate a second carry signal according to a last refresh pulse signal generated by the received refresh command; a first counter that is configured to perform signal inversion according to the first carry signal and generate a first output signal; and a second counter that is configured to count the refresh command according to the second carry signal and generate a second output signal; where the refresh command generates at least two refresh pulse signals.

Abstract: Disclosed herein are novel Pichia pastoris strains for expression of exogenous proteins with substantially homogeneous N-glycans. The strains are genetically engineered to include a mutant OCH1 allele which is transcribed into an mRNA coding for a mutant OCH1 gene product (i.e., ?-1,6-mannosyltransferase, or “OCH1 protein”). The mutant OCH1 protein contains a catalytic domain substantially identical to that of the wild type OCH1 protein, but lacks an N-terminal sequence necessary to target the OCH1 protein to the Golgi apparatus. The strains disclosed herein are robust, stable, and transformable, and the mutant OCH1 allele and the ability to produce substantially homogeneous N-glycans are maintained for generations after rounds of freezing and thawing and after subsequent transformations.

Abstract: The present application provides a parameter setting method and apparatus, a system, and a storage medium. The parameter setting method includes: obtaining first setting values of multiple memory parameters and storage locations of the multiple memory parameters in a non-volatile memory; generating a first parameter setting instruction according to the first setting value and the storage location of each memory parameter; and sending the first parameter setting instruction to a test device, so that the test device sets the memory parameter stored at the storage location in the non-volatile memory as the first setting value.

Abstract: Homopolar linear synchronous machines are provided herein that include a mover device. The mover device includes a cold plate with ferromagnetic cores extending through slots in the cold plate. Layers of armature coils are located around the ferromagnetic cores on opposite sides of the cold plate. The mover device further includes at least one field coil.

Abstract: A laminated capacitor and a method for manufacturing the same are provided. The method includes operations of providing a substrate; forming a first isolation insulation spacer and a plurality of discrete bottom bonding pads on the substrate; forming a sub-capacitor structure on the bottom bonding pads, which comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium located between the bottom electrodes and the top electrodes, wherein the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes in one-to-one correspondence; and repeatedly performing an operation of forming a connection structure and the sub-capacitor structure for N times on the sub-capacitor structure, such that N connection structures and N+1 sub-capacitor structures are alternately arranged along a direction perpendicular to the substrate, wherein N is an integer greater than or equal to 1.

Abstract: A miniature radar target simulator (MRTS) and a system comprising a plurality of MRTS's are described. The MRTS and system are useful for emulating echo signals for a radar DUT with reduced interference. Illustrative radar test systems desirably generate the intended (emulated) radar targets and reduce unwanted (“ghost”) signals, which can result in “ghost targets,” and errant/ambient electromagnetic radiation that reduces the performance and reliability of known re-illuminators and systems including same.

Abstract: An aircraft engine fire extinguishing system includes a supply housing for containing a fire extinguishing agent. Also included is a line for routing the fire extinguishing agent from the supply housing. Further included is a nozzle structure operatively coupled to the line, the nozzle structure having a non-circular opening for expelling the fire extinguishing agent.

Abstract: A method for improving an etching rate of wet etching involves an etching reaction chamber used for etching work. The etching reaction chamber is connected with an etchant supply mechanism. The etchant supply mechanism is connected with a purified water supply mechanism. The purified water supply mechanism injects purified water into the etchant supply mechanism according to a change range of pH of the etchant in the etchant supply mechanism to ensure that a hydrogen ion concentration and a fluoride ion concentration of the etchant in the etchant supply mechanism are stable.

Abstract: Provided are a parasitic capacitance detection method, a memory, and a readable storage medium, relating to the field of semiconductor technologies. The detection method comprises: providing a plurality of semiconductor devices for testing, all the semiconductor devices being the same in a number of sources, a number of drains, a number of active layers, a number of gates, a number of wires and a cross-sectional area of the wire, all the semiconductor devices being different in a length of the wire therein; determining a capacitance between the wire per unit length and the gate in the semiconductor device, the capacitance between the wire per unit length and the gate being considered as a parasitic capacitance per unit length; determining a corresponding wire length of a to-be-detected semiconductor device; and determining a parasitic capacitance of the to-be-detected semiconductor device.

Abstract: A word line driving circuit includes a driving circuit and a control circuit. The control circuit includes a control sub-circuit, a first switching sub-circuit and a second switching sub-circuit. The first switching sub-circuit is provided with: a control terminal electrically connected with the control sub-circuit, a first terminal electrically connected with a first power supply voltage, and a second terminal electrically connected with a third input terminal of the driving circuit. The second switching sub-circuit is provided with: a control terminal electrically connected with the control sub-circuit, a first terminal electrically connected with a second power supply voltage, and a second terminal electrically connected with the third input terminal of the driving circuit. The second power supply voltage is greater than a ground voltage.

Abstract: A memory bank includes at least one storage module, each storage module including a read-write control circuit, a column decoding circuit and a plurality of storage arrays, the plurality of storage arrays being divided into a first unit and a second unit; a first decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the first unit; a second decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the second unit; a first data signal line; and a second data signal line.

Abstract: A semiconductor device includes a substrate including a memory region and a peripheral region located at an outer side of the memory region; a memory structure located above the memory region and including a memory array and signal lines, the memory array at least including memory cells spaced apart from each other along a first direction, and the signal lines being electrically connected with the memory cells, the first direction is perpendicular to the top surface of the substrate; a peripheral structure located above the peripheral region and including peripheral stacked layers, peripheral circuits located above the peripheral stacked layer, and peripheral leads located above the peripheral circuits, one end of each peripheral lead being electrically connected with at least one of peripheral circuits, and the other end being electrically connected with at least one of signal lines.