Abstract: The present disclosure provides a process variation detection circuit and a process variation detection method. The process variation detection circuit is arranged in a chip and includes: a first ring oscillator, where a first number of auxiliary elements of a preset type are arranged between two adjacent inverters of the first ring oscillator; and a second ring oscillator, where a second number of auxiliary elements of a preset type are arranged between two adjacent inverters of the second ring oscillator, the second number is larger than the first number; wherein, a number of the inverter of the first ring oscillator is the same as a number of the inverter of the second ring oscillator; a type and a size of a transistor of the first ring oscillator are the same as a type and a size of a transistor of the second ring oscillator.

Abstract: The present application provides an output driving circuit and a memory. The output driving circuit includes: a signal input terminal inputting a positive input signal and a negative input signal complementary to each other; a pull-up output unit and a pull-down output unit connected to the signal input terminal, the positive input signal acting as an input signal of the pull-up output unit, and the negative input signal acting as an input signal of the pull-down output unit; at least one compensation unit connected in parallel with the pull-up or pull-down output unit; at least one pulse signal generation circuit, and generating a pulse signal, the pulse signal acting as a control signal of the compensation unit; and a signal output terminal connected to an output terminal of the pull-up output unit, an output terminal of the pull-down output unit and an output terminal of the compensation unit.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for externally held account discovery and aggregation. A method includes aggregating transactions of a first service provider from one or more servers to a trusted hardware device. A method includes identifying, on a trusted hardware device, one or more transactions of a first service provider between an account of a user with the first service provider and an account of the user with a second service provider. A method includes prompting a user for electronic credentials for an account of the user with a second service provider. A method includes accessing data of a user from a second service provider on behalf of the user using electronic credentials.

Abstract: A system and method for low-distortion compaction of floating-point numbers comprising a pre-encoder, a data deconstruction engine, a library manager, a codeword storage, and a data reconstruction engine. A pre-encoder may receive a plurality of data sourcepackets with may contain one or more floating-point numbers and the received data sourcepackets are scanned to identify floating-point numbers and the identified floating-point numbers. Identified floating-point numbers may be pre-encoded into binary string representations which are low-distortion embeddings of real numbers into a Hamming space. The binary string representation may be indexed to indicate it represents a floating-point number before being compacted by a data deconstruction engine and library manager. The pre-encoding of floating-point numbers located within a sourcepacket enables the system to maximize the benefit of the compaction capabilities of the data deconstruction engine.

Abstract: An anti-fuse unit and an anti-fuse array. The anti-fuse unit includes an anti-fuse device and a diode. An anode of the anti-fuse device is electrically connected with a bit line, a cathode of the anti-fuse device is electrically connected with an anode of the diode, and a cathode of the diode is electrically connected with a word line.

Abstract: Embodiment relates to the field of semiconductor technologies, and proposes a semiconductor device and a fabrication method thereof. The semiconductor device includes: a substrate, a semiconductor structure, an insulating layer, and a conductive layer. The semiconductor structure is positioned on a side of the substrate and includes a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure form a PN junction. The insulating layer is positioned on a side of the semiconductor structure facing away from the substrate. The conductive layer is positioned on a side of the insulating layer facing away from the substrate, and an orthographic projection of the conductive layer on the substrate at least partially overlaps an orthographic projection of the PN junction on the substrate.

Abstract: A refresh control circuit includes: a random output sub-circuit for sequentially receiving n single-row addresses and m single-row addresses in L single-row addresses, a single enabling duration of word lines pointed to by the n single-row addresses being greater than a preset duration, the m single-row addresses ranking top m in occurrence frequency, the L single-row addresses corresponding to word lines turned on between adjacent refresh commands, n being a natural number, and m being a positive integer; and for receiving a first random number which is a positive integer less than or equal to n+m, and then outputting an i-th received single-row address, i being equal to the first random number; and a row hammer address generation sub-circuit for outputting a row hammer address corresponding to the received single-row address acting as a refresh object corresponding to the refresh command.

Abstract: A sense amplifier includes: an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit, wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell.

Abstract: A fire suppression system includes a feed port and a channel to couple the feed port to an actuation chamber. A solenoid valve controllably blocks a connection between the feed port and the channel. Pressure from the feed port builds up in the actuation chamber based on the solenoid valve unblocking the connection. A piston is in communication with the actuation chamber. The system also includes an inlet port closed off by a disc. The piston travels through the inlet port and burst the disc based on the pressure in the actuation chamber. An outlet port is coupled to the inlet port.

Abstract: The present application provides a wafer cleaning equipment and a wafer cleaning method. During wafer cleaning operation, the landing position of a cleaning agent sprayed by a nozzle onto the surface of a wafer can be detected, and when the landing position produces a deviation, the measures of controlling a nozzle adjusting mechanism to adjust the position and/or spray angle of the nozzle, controlling a flow rate adjusting unit to adjust the flow rate of the cleaning agent sprayed by the nozzle, etc. are taken, so that the landing position of the cleaning agent sprayed by the nozzle onto the surface of the wafer is within a preset target region.

Abstract: The embodiments provide a method for reading and writing and a memory device. The method for reading and writing includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and associating the address information pointed to by the read command with a spare memory cell if an error occurs in the data to be read out. The method for reading and writing provided by the present disclosure greatly improves reliability of the memory device and prolongs lifespan of the memory device.

Abstract: A method of forming a semiconductor structure and the semiconductor structure are provided. The method includes the following operations. A semiconductor substrate is provided, in which a plurality of isolation grooves distributed at intervals are provided in the semiconductor substrate, and each of the isolation grooves includes a top region isolation groove and a bottom region isolation groove. A first protective layer covering the side wall of the top region isolation groove and the top of the semiconductor substrate is formed. Oxidation treatment is performed on the bottom region isolation groove to oxidize a part of the semiconductor substrate close to the bottom region isolation groove to form a second substrate isolation layer. A dielectric layer filling the isolation groove is formed. The first protective layer and the dielectric layer higher than the top of the semiconductor substrate are etched to form an isolation structure.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming an initial trench in the substrate; forming a sacrificial layer, the sacrificial layer including a first portion and a second portion, the first portion filling the initial trench and the second portion covering an upper surface of the substrate and an upper surface of the first portion; forming a division groove in the second portion, to pattern the second portion into a sacrificial pattern, the sacrificial pattern being arranged corresponding to the first portion; forming a filling layer in the division groove, the filling layer filling the division groove; removing the sacrificial pattern and the first portion, to form a word line trench; and forming a buried gate word line in the word line trench.

Abstract: A storage device includes a storage circuit, a reading circuit, a first check circuit, and a second check circuit. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays which are arranged alternately. A first data wire is electrically connected to each of the sense amplifier arrays. The reading circuit is configured to read data on the first data wire. Both the first check circuit and the second check circuit are electrically connected to the reading circuit. The reading circuit is configured to transmit a part of the read data to the first check circuit for error checking and/or correcting, and transmit another part of the read data to the second check circuit for error checking and/or correcting. The data transmitted to the first check circuit and the data transmitted to the second check circuit are respectively from adjacent sense amplifier arrays.

Abstract: A neural network is trained to process input data and generate a classification value that characterizes the input with respect to an ordered continuum of classes. For example, the input data may comprise an image and the classification value may be indicative of a quality of the image. The ordered continuum of classes may represent classes of quality of the image ranging from “worst”, “bad”, “normal”, “good”, to “best”. During training, loss values are determined using an ordered classification loss function. The ordered classification loss function maintains monotonicity in the loss values that corresponds to placement in the continuum. For example, the classification value for a “bad” image will be less than the classification value indicative of a “best” image. The classification value may be used for subsequent processing. For example, biometric input data may be required to have a minimum classification value for further processing.

Abstract: The application provides a method for manufacturing a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors. The method for manufacturing the semiconductor structure includes: providing a base; sequentially stacking an initial conductive layer, an initial first dielectric layer, an initial first mask layer, an initial second dielectric layer, an initial second mask layer and a photoresist layer with a pattern on the base; and etching part of the initial second mask layer, part of the initial second dielectric layer and part of the initial first mask layer by taking the photoresist layer as a mask, so as to form a second dielectric layer with a trapezoidal structure which is of a structure with small top and large bottom.

Abstract: A method for forming a semiconductor structure and a semiconductor structure are provided. The method includes: a stacked structure is formed on a surface of a substrate, the stacked structure including supporting layers and sacrificial layers which are alternately stacked; a buffer layer is formed on a surface of the stacked structure facing away from the substrate; capacitor holes penetrating through the stacked structure and the buffer layer and exposing capacitor contacts are formed; a first electrode layer covering inner walls of the capacitor holes is formed; an etching window penetrating through the buffer layer is formed; part of the supporting layers and all of the sacrificial layers in the stacked structure are removed along the etching window; the buffer layer is removed; and a dielectric layer and a second electrode layer are formed to form a capacitor.

Abstract: Disclosed are various embodiments for interfaces for creating radio-based private networks. In one embodiment, a request is received via an interface to create a radio-based private network for a customer. The request indicates a quantity of wireless devices that will connect to the radio-based private network. A quantity of radio units to serve the radio-based private network is determined based at least in part on the quantity of wireless devices. The radio units are preconfigured to implement a radio access network for the radio-based private network. A shipment is initiated to the customer of the radio units that have been preconfigured. Resources in a cloud provider network are provisioned to function as a core network for the radio-based private network.