Patents Assigned to TECHNOLOGIES INC.
  • METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
    Publication number: 20240008248
    Abstract: A method for manufacturing a semiconductor structure includes the following operations. A structure to be etched is provided. An etched hole is formed in the structure to be etched. Multiple conducting material layer deposition processes are performed until the conducting material layer fills up the etched hole without a void. The method further includes annealing the deposited conducting material layer after at least some of the conducting material layer deposition processes.
    Type: Application
    Filed: January 13, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: YOUMING LIU
  • PROCESSES FOR USING TEMPERATURE MEASUREMENTS TO DETERMINE HEALTH METRICS
    Publication number: 20240000440
    Abstract: A process for using temperature measurements to determine health metrics includes: a) using a first temperature sensor of a wearable device to obtain a first set of measurements at a first location on a user's body over a time period; b) using a second temperature sensor of the wearable device to obtain a second set of measurements at a second location on the user's body over the time period; c) processing the measurements to identify changes in temperature over the time period, determining a first health metric based on the changes, and outputting an indication of the first health metric; and d) processing the measurements to compare the temperature at the first location at a given time point to the temperature at the second location at the given time point, determining a second health metric based on the comparison, and outputting an indication of the second health metric.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: ORPYX MEDICAL TECHNOLOGIES INC.
    Inventors: JULIA BREANNE EVERETT, TRAVIS MICHAEL STEVENS
  • SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND MEMORY
    Publication number: 20240006175
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes: a substrate is provided, the substrate being provided with a first device area and a second device area with different doping types; a gate oxide layer which covers the first device area and the second device area is formed; a gate conductive layer which covers the gate oxide layer is formed; a first gate structure is formed on the first device area, the first gate structure including the gate conductive layer and the gate oxide layer; a second gate structure is formed on the second device area, the second gate structure including the gate conductive layer and the gate oxide layer. In the first device area and the second device area, the gate conductive layer always covers the gate oxide layer.
    Type: Application
    Filed: January 17, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kang You, Jie Bai
  • SEMICONDUCTOR STRUCTURE, PACKAGING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
    Publication number: 20240006281
    Abstract: A semiconductor structure includes: a substrate including a first surface; a first solder pad located on the first surface; a transferring part located on the first solder pad, in which the transferring part includes a first subpart covering the first solder pad and a second subpart covering the first subpart, and orthographic projections of the first subpart and the first solder pad on the first surface fall within an orthographic projection of the second subpart on the first surface; and a solder ball located on the second subpart.
    Type: Application
    Filed: January 20, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zongzheng LU
  • SEMICONDUCTOR STRUCTURE, FABRICATION METHOD FOR SEMICONDUCTOR STRUCTURE AND MEMORY
    Publication number: 20240006319
    Abstract: A semiconductor structure includes a base provided with a conductive contact hole, a metal sulfide layer formed in the conductive contact hole and covering a bottom wall of the conductive contact hole, a semi-metal layer formed on a surface of the metal sulfide layer, a barrier layer covering a surface of the semi-metal layer and a sidewall of the conductive contact hole and a conductive contact structure disposed in an accommodation hole delimited by the barrier layer.
    Type: Application
    Filed: August 11, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shuai GUO
  • DECENTRALIZED CONSENT NETWORK FOR DECOUPLING THE STORAGE OF PERSONALLY IDENTIFIABLE USER DATA FROM USER PROFILING DATA
    Publication number: 20240005020
    Abstract: A computer implemented method for tracking and securing user data, the method including providing a user data vault that stores user data, providing the user data to display on a user interface, collecting access rights and permission settings, storing the access rights on a blockchain consent network, and providing access to remote users. The system and methods utilize blockchain technology, encryption, and a novel data structure (e.g. consent tokens) that enhance the security, transparency, and user experience regarding user data collection.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 4, 2024
    Applicant: CONCORD TECHNOLOGIES INC.
    Inventors: Dashiell LAVINE, Paul LAWBAUGH, Cian MONTGOMERY
  • REPAIR OF OVARIAN DAMAGE AND DAMPENING OF INFLAMMATORY MICROENVIRONMENT BY ADMINISTRATION OF MONOCYTIC-GRANULOCYTIC PROGENITORS WITH IMMUNE MODULATORY ACTIVITIES
    Publication number: 20240002792
    Abstract: The invention provides means, methods and some compositions of matter useful to treat ovarian failure. In one embodiment progenitor cells possessing ability to differentiate along the monocytic and granulocyte linages are utilized as a source of cytokines for stimulation of ovarian repair/regeneration. Generation of said cells, such as classically termed myeloid derived suppressor cells is performed from sources including cord blood, bone marrow, mobilized peripheral blood and pluripotent stem cells. The invention further provides means of suppressing fibrosis and ongoing inflammation associated with ovarian dysfunction.
    Type: Application
    Filed: May 16, 2023
    Publication date: January 4, 2024
    Applicant: CREATIVE MEDICAL TECHNOLOGIES, INC.
    Inventors: Thomas ICHIM, Amit PATEL, Courtney BARTLETT
  • SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREFOR, AND MEMORY
    Publication number: 20240008376
    Abstract: A semiconductor structure includes a substrate and a phase-change memory cell located on the substrate. The phase-change memory cell includes a phase-change material layer and a heating layer. The heating layer is located between the phase-change material layer and the substrate, and includes a first portion composed of a first conductive material and a second portion composed of a second conductive material. The first portion surrounds at least a sidewall of the second portion.
    Type: Application
    Filed: January 17, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: YU-CHENG LIAO
  • ANTI-FUSE CELL STRUCTURE, ANTI-FUSE ARRAY, OPERATION METHOD FOR ANTI-FUSE ARRAY, AND MEMORY
    Publication number: 20240006006
    Abstract: An anti-fuse cell structure includes: a first anti-fuse transistor having a first end and a second end; a first selection transistor having a first end and a second end, the first end of the first selection transistor being electrically connected to the second end of the first anti-fuse transistor; and a Blow Enable (BE) line electrically connected to a first end of the first anti-fuse transistor, and configured to perform programming operation on the first anti-fuse transistor.
    Type: Application
    Filed: April 4, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.,
    Inventor: Chuangming HOU
  • UNIVERSAL MULTI-DETECTION SYSTEM FOR MICROPLATES WITH CONFOCAL IMAGING
    Publication number: 20240003810
    Abstract: An apparatus for optically analyzing a sample may include an imaging subsystem that images the sample, one or more analyzing subsystems that analyze the sample including a confocal imaging subsystem, a temperature control subsystem that controls a temperature of the atmosphere within the apparatus, a gas control subsystem that controls a composition of the atmosphere within the apparatus, and a control module that controls the various subsystems of the apparatus.
    Type: Application
    Filed: December 2, 2021
    Publication date: January 4, 2024
    Applicant: AGILENT TECHNOLOGIES, INC.
    Inventors: Ross Marcel PIETTE, Xavier Francois Patrick AMOURETTI, Caleb Alan FOSTER, Benjamin Jon KNIGHT, Peter Brent KNOX, Ben Edward NORRIS, James Donald PIETTE, Richard Niles SEARS, Matthew Arthur STILES, Oleg Nikolaevich ZIMENKOV
  • ANALYTE DETECTION SYSTEM AND CONTINUOUS GLUCOSE MONITORING DEVICE
    Publication number: 20240000398
    Abstract: An analyte detection system, includes a bottom case housing, which is used for mounting to the surface of human skin; a sensor mounted on the bottom case housing for detecting the analyte parameter information; a transmitter unit including a transmitters shell, an internal circuit, a transmitter and a motion sensor, the transmitter sending the analyte parameter information to the outside world, the motion sensor connected to the internal circuit operationally, used for induction or identify the user's body movements. According to induction or recognition of body movements by the motion sensor, the internal circuit controls the sensor or the transmitter to execute the corresponding functional instructions to enhance the user experience.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 4, 2024
    Applicant: MEDTRUM TECHNOLOGIES INC.
    Inventor: Cuijun Yang
  • METHOD AND APPARATUS FOR CHECKING DATA PROCESSING CIRCUIT, AND ELECTRONIC DEVICE
    Publication number: 20240005072
    Abstract: A method for checking a data processing circuit includes the following. Performance check files of a plurality of timing sequence logic elements in the data processing circuit are acquired, and the data processing circuit is simulated based on the performance check files of the plurality of timing sequence logic elements, so as to obtain timing sequence information of the respective timing sequence logic elements.
    Type: Application
    Filed: January 31, 2023
    Publication date: January 4, 2024
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zengquan WU
  • Memory and method for manufacturing same
    Patent number: 11864375
    Abstract: A memory and a method for manufacturing the same are provided. The memory includes: a substrate including an isolation structure and an active area between adjacent isolation structures; a first gate structure, the first gate structure locates in a first groove of the isolation structure, includes a first gate filled in the first groove, and the first gate includes a first conductive layer filled at the bottom of the first groove and a second conductive layer, the second conductive layer locates above the first conductive layer, and the work function of the material of the first conductive layer is greater than that of the material of the second conductive layer; a second gate structure, located in the second groove of the active area, includes a second gate filled in the second groove, and the material of the second gate is the same as that of the second conductive layer.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: ChihCheng Liu
  • Bit line sense circuit and memory
    Patent number: 11862239
    Abstract: A bit line sense circuit and a memory are disclosed in the present application. The bit line sense circuit includes: L storage unit groups, each storage unit group including H bit lines, both L and H being positive integers greater than or equal to 2; and M sense amplifier groups, configured to write or read storage data to or from the bit lines in the storage unit groups and electrically connected to the L storage unit groups, M being an integer multiple of L or L being an integer multiple of M. Two adjacent bit lines of the H bit lines are connected to the different sense amplifier groups.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Sungsoo Chi, Jia Wang, Ying Wang, Shuyan Jin, Fengqin Zhang
  • Asymmetrical magnet arrays
    Patent number: 11862391
    Abstract: Magnet array structure includes a first linear magnet array and a second linear magnet array having a first and a second arrangement of magnets, respectively, in which the first and the second arrangement of magnets are repeated along respective lengths of the first and second linear magnet array. The first and second arrangement of magnets include respective individual first and second magnet elements arranged along the respective length of the first and second linear magnet array so that no net magnetic forces parallel to the length of the first and second linear magnet array result on the first and second arrangement of magnets, respectively. The first arrangement of magnets is offset from the second arrangement of magnets so that the first arrangement of magnets and the second arrangement of magnets partially overlap.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: January 2, 2024
    Assignee: HYPERLOOP TECHNOLOGIES, INC.
    Inventor: Casey Handmer
  • Method of forming oxide layer on a doped substrate using nitridation and oxidation process
    Patent number: 11862461
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a base is provided, in which the base includes a first doped area and a second doped area, and an isolation structure is provided between the first doped area and the second doped area; nitridation treatment is performed on the first doped area and the second doped area; and oxidation treatment is performed on the first doped area and the second doped area subjected to the nitridation treatment, to form a first gate oxide layer and a second gate oxide layer respectively.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Tzung-Han Lee
  • Memory chip and memory system
    Patent number: 11862290
    Abstract: A memory chip stores a characterization parameter for characterizing a process corner of the memory chip, the memory chip further has a reference voltage with an adjustable value, the value of the reference voltage is adjustable based on the characterization parameter, and the memory chip adjusts, based on the reference voltage, a delay from reading out data from a memory cell to outputting the data through a data port.
    Type: Grant
    Filed: April 30, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Memory test method, memory test apparatus, device and storage medium
    Patent number: 11860748
    Abstract: A memory test method, a memory test apparatus, a device and a storage medium are provided. The memory test method includes: obtaining a central processing unit (CPU) accessible space of a memory to-be-tested; obtaining a graphics processing unit (GPU) accessible space of the memory to-be-tested; and driving a CPU to run a test program based on the accessible space of the CPU, to access the memory to-be-tested through a bus of memory to-be-tested, when the CPU runs the test program, the CPU controls a GPU to access the memory to-be-tested based on the accessible space of the GPU through the bus of memory to-be-tested.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiaofeng Xu
  • System and method for detecting mismatch of sense amplifier
    Patent number: 11862233
    Abstract: The present application relates to the field of semiconductors, in particular, to the field of Dynamic Random Access Memories (DRAMs), and provides a method and system for detecting a mismatch of a sense amplifier. The method creates a sense amplifier by delaying switch-on of a positive channel-metal-oxide-semiconductor (PMOS) transistor or a negative channel-metal-oxide-semiconductor (NMOS) transistor in the sense amplifier and shortening a row precharge command period (tRP).
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Dong Liu, Tianhao Diwu, Xikun Chu
  • Time offset method and device for test signal
    Patent number: 11860226
    Abstract: Embodiments of the present application provide a time offset method and device for a test signal. When a signal source sends a test signal to a DUT on a test platform, the offset device can determine a time delay caused by impedance matching of the test signal to the DUT at the upper side of each test location, and conduct time offset for TCK signals sent by the signal source to different DUTs according to the time delay.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Liang Chen, Xuemeng Lan