Abstract: A system uses an obstacle map to determine an avoidance map that indicates one or more constraint regions that are present in a physical space. The obstacle map is processed using a smoothing function and the smoothed map processed with a medial axis transform function to generate a MAT skeleton. The skeleton is pruned to remove spurs and then segmented based on MAT values that are representative of distances in the physical space between the skeleton and an obstacle. The avoidance map is determined by associating constraint regions with the segments. Constraint regions may indicate areas in the physical space that are open for the autonomous mobile device (AMD) to stop, narrow areas for which stopping should be avoided, and closed areas within which the AMD is not to stop during ordinary operation.

Abstract: Methods, systems, and computer readable media for exposing data processing unit (DPU) traffic in a smartswitch are disclosed. One example method occurs at a smartswitch controller implemented using at least one processor, the method comprising: receiving connection information for communicating with an in-line traffic processing agent; generating, using the connection information, one or more switching rules for causing traffic associated with a target DPU of a smartswitch to be directed to the in-line traffic processing agent; and providing the one or more switching rules to the smartswitch or another entity.

Abstract: Memory includes at least one memory chip, a command port and a data port. Each memory chip includes at least one channel. Each channel includes multiple banks that are configured to perform read and write operations alternately. The command port is configured to receive command signals at a preset edge of a command clock, and the command signals are configured to control the read and write operations of the banks. The data port is configured to receive data signals to be written into the banks or transmit data signals at preset edges of a data clock. The command port includes a row address port and a column address port. The row address port is configured to receive a row address signal at a position of a target memory cell, and the column address port is configured to receive a column address signal at a position of the target memory cell.

Abstract: A respiratory treatment apparatus generates an indication of inspiration or expiration based on a measure of motor current of a flow generator. In an example, first and second current signals are derived from the measurement. The first derived current signal may be a long term measure or average of current and the second derived current signal may be a short term measure or average of current. A processor 120 determines an indication of inspiration or expiration as a function of the first and second derived current signals. The function of the first derived current signal and the second derived current signal may be a comparison of the derived current signals. The derived signals may be determined by filtering. The indication of inspiration or expiration may serve as a trigger or cycle control for changing treatment pressure in synchrony with patient respiration without measured signals from pressure, flow or speed sensors.

Abstract: A flow control device includes a flow shield defining a volume and a plurality of shield openings of the flow shield arranged such that gas entering the volume must pass through at least one of the plurality of shield openings. The flow control device also includes a flow restrictor to define an opening for the gas exiting the volume.

Abstract: Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.

Abstract: A data sampling circuit includes a frequency dividing circuit, a sampling circuit and a selection circuit. The frequency dividing circuit is configured to receive a first data sampling signal, and perform frequency dividing processing on the first data sampling signal to obtain multiple second data sampling signals associated with respective phases; the sampling circuit is configured to receive the multiple second data sampling signals and a first data signal, and sample the first data signal according to the multiple second data sampling signals to obtain multiple second data signals associated with respective phases; and the selection circuit is configured to receive preamble information and mode register set (MRS) information, and select among the multiple second data sampling signals and the plurality of second data signals according to the preamble information and the MRS information to obtain a target data sampling signal and a target data signal respectively.

Abstract: The presently disclosed subject matter generally relates to recyclable insulation material for shipping containers, groceries bags, etc., machines for making the recyclable insulation material, and methods for the making the recyclable insulation material. In one aspect, a method of forming an insulation product may include forming a continuous sheet of paper into a plurality of flexible loops defining a plurality of air channels extending in a direction that is substantially perpendicular with a machine direction of the continuous sheet of paper. The method may also include immediately attaching a first layer of paper and a second layer of paper to the plurality of flexible loops as they are formed so that the continuous sheet of paper retains the plurality of flexible loops between the first layer and the second layer and that the plurality of flexible loops remain unattached with respect to one another.

Abstract: Methods for measuring a temperature of a wafer chuck and calibrating temperature and a temperature measuring system are provided. The measuring method includes: placing a test wafer on a wafer chuck, where a plurality of semiconductor devices having electrical parameters varying as a function of temperature are formed on the test wafer; making the temperature of the wafer chuck reach set temperatures; measuring the semiconductor devices respectively to obtain electrical parameters corresponding to the semiconductor devices; obtaining actual temperatures of the semiconductor devices according to the electrical parameters and variations, of the electrical parameters, as the function of temperature; and obtaining an actual temperature distribution of the wafer chuck according to the actual temperatures of the semiconductor devices.

Abstract: A method of frequency-converting a received radio frequency (RF) signal includes frequency mixing a received RF signal with a first local oscillator (LO) signal to generate a first intermediate frequency (IF) signal, where the first IF signal is a mixed signal of a desired signal and an image signal. The method further includes frequency mixing the RF signal with a second LO signal to generate a second IF signal, where the second LO signal has a same frequency as the first LO signal, and the second LO signal has a 90 degree phase shift relative to the first LO signal.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The method of manufacturing the semiconductor structure includes: providing a substrate; forming, on the substrate, a first initial conductive layer, a sacrificial layer and a first mask layer with a pattern that are stacked sequentially, a thickness of the sacrificial layer being 10 nm-20 nm; and etching, with the first mask layer as a mask, the first initial conductive layer and the substrate to form a bit line (BL) contact region.

Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Abstract: The present application provides a comparison method and a modeling method for a chip product, a device and a storage medium. According to the method, the chip product is modeled by using a neural network based on a slice sequence of the chip product in advance to obtain a three-dimensional stereoscopic model. When the chip products are compared, a comparison feature is acquired responsive to an operation of a user. For each chip product, a comparison result corresponding to the comparison feature is acquired from the three-dimensional stereoscopic model corresponding to each chip product. Then, the comparison result corresponding to each chip product is displayed.

Abstract: Embodiments of the present application provide a memory structure and a memory layout. The memory structure includes: memory arrays, each including a plurality of memory cells; read-write conversion circuits, each disposed between two adjacent ones of the memory arrays in a first direction, being arranged in a second direction, having a symmetry axis in the second direction, and configured to write external data into the memory cells, or read data from the memory cells, and the first direction being perpendicular to the second direction; sense amplification circuits, symmetrically disposed between two adjacent ones of the memory arrays based on the symmetry axis, coupled to the memory cells in the adjacent ones of the memory arrays; and bias contact point structures, disposed in gaps between the read-write conversion circuits, and configured to set a bias voltage of a well region where the bias contact point structures are located.

Abstract: A method for isolating transmission lines of a radio frequency power amplifier and a transmission structure of the radio frequency power amplifier are provided. The method includes steps of setting a distance between adjacent two of transmission lines on a chip substrate to be greater than 2.5 times a width of each of the transmission lines, and disposing shielding lines at an inner side of each of the transmission lines and an outer side of each of the transmission lines opposite to the inner side; wrapping a permalloy layer on an outer wall of each of the transmission lines; and wrapping an aluminum layer on an outer wall of the permalloy layer, defining a plurality of grooves on an outer wall of the aluminum layer at intervals, where the plurality of the grooves are recessed inward and in an inverted triangular structure.

Abstract: A camera acquires an image of an item involved in an interaction, such as the item being picked or placed on a shelf by a user. The item depicted in the image is identified via item recognition using a customized neural network that uses previously trained subnetworks for a set of candidate items. The candidate items are determined based on items near a user location, items associated with a user cart, items in a shopping list or wish list associated with the user, or items otherwise associated with the user. Each previously trained subnetwork for a candidate item includes one or more reference images and corresponding reference feature data. The customized neural network uses a matching and inference network to test the image against the candidate items and provide comparison data indicative of a similarity between the item depicted in the image and one of the candidate items.

Abstract: A driving mechanism of a drug infusion device, includes at least one driving unit and at least one driving wheel, the driving unit, moving in the driving direction, driving the driving wheel to rotate; a linear actuator, electrically connected with the driving unit, pulling the driving unit to move in the driving direction after being powered; a switch unit group, including a first switch unit and a second switch unit, the first switch unit electrically connected with the linear actuator; a power supply, the power supply, the switch unit group and the linear actuator electrically connected to form a power supply circuit that supplies power to the linear actuator; when the linear actuator being powered, the driving unit implementing driving, and the driving unit triggering a first signal, indicating the end point of the driving direction.

Abstract: A memory chip test method includes: a mode register write command is sent to a memory chip to control a memory chip to enter a test mode of Write Clock to clock leveling (Wck2ck Leveling); a first preset time is set, and a read and write clock signal is sent to the memory chip after waiting for the first preset time; a predicted value of the Wck2ck Leveling is determined according to the first preset time and a system clock cycle; after sending the read and write clock signal and waiting for a second preset time, a test data output port of the memory chip is detected to obtain a test value; and the test value and the predicted value are compared to determine whether the memory chip is abnormal. A method for testing a Wck2ck Leveling function is provided.

Abstract: Disclosed are novel cellular compositions of matter and treatment means for generation of universal donor regenerative T cells by exposure to mesenchymal stem cells or supernatant derived thereof. In one embodiment, regenerative T cells are created by differentiation of pluripotent stem cells in the presence of supernatant generated from activated mesenchymal stem cell population. The invention provides for creation of T cells which are capable of endowing regenerative activity, and/or anti-inflammatory, and/or angiogenic activity.

Abstract: A semiconductor device includes: a power down control circuit receiving a power down command signal and a chip selection signal, and generating a power down enable signal and a power down exit signal, here, a logic level of the power down enable signal is converted at a first edge of the power down command signal during a power down stage, and a logic level of the power down exit signal is converted at a second edge of the chip selection signal during a power down exit stage; a power control circuit stopping providing a power voltage according to the power down enable signal during the power down stage, and providing the power voltage according to the power down exit signal during the power down exit stage; and an input buffer circuit transmitting signals during the power down exit stage in response to the power down exit signal.