Patents Assigned to TECHNOLOGIES INC.
-
Patent number: 11853591Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on a first sub-data to generate a second encoded data, and transmit a second data to a memory die in the writing phase; where the second data includes the first sub-data, a second sub-data, the first encoded data, and the second encoded data; the base die is further configured to: receive the second data from the memory die in a reading phase, perform first error checking and correction processing on the first sub-data and the second encoded data, and transmit a third data in the reading phase.Type: GrantFiled: May 1, 2022Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shu-Liang Ning
-
Patent number: 11853551Abstract: The embodiments of the present disclosure relate to the technical field of semiconductors and provide a storage system and a data reading method thereof. The storage system is configured to: enter a read data copy mode in response to a read-copy enable signal; if at least two groups of data in multiple groups of data exported from a memory array are a same in the read data copy mode, define the at least two groups of data as a category; export an identification signal that is used to indicate a data copy; transmit one group of data in the category to a corresponding data port; and disconnect a transmission path that is used to transmit another group of data in the category to a corresponding data port.Type: GrantFiled: April 4, 2022Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Kangling Ji
-
Patent number: 11851652Abstract: Provided herein are methods for inducing CRISPR/Cas-based gene regulation (e.g., genome editing or gene expression) of a target nucleic acid (e.g., target DNA or target RNA) in a cell. The methods include using modified single guide RNAs (sgRNAs) that enhance gene regulation of the target nucleic acid in a primary cell for use in ex vivo therapy or in a cell in a subject for use in in vivo therapy. Additionally, provided herein are methods for preventing or treating a genetic disease in a subject by administering a sufficient amount of a modified sgRNA to correct a mutation in a target gene associated with the genetic disease.Type: GrantFiled: March 14, 2022Date of Patent: December 26, 2023Assignees: THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR, UNIVERSITY and AGILENT TECHNOLOGIES, INC.Inventors: Matthew H. Porteus, Ayal Hendel, Joe Clark, Rasmus O. Bak, Daniel E. Ryan, Douglas J. Dellinger, Robert Kaiser, Joel Myerson
-
Patent number: 11856758Abstract: A method for manufacturing a memory includes: providing a substrate and multiple discrete pseudo bit line contact layers, a plurality of active areas being provided in the substrate, and each bit line contact layer being electrically connected to the active areas; forming pseudo bit line structures at tops of the pseudo bit line contact layers; forming sacrificial layers that fill regions between the adjacent pseudo bit line structures and are located on side walls of the pseudo bit line structures and the pseudo bit line contact layers; after forming the sacrificial layers, removing the pseudo bit line structures to form through holes exposing the pseudo bit line contact layers; removing the pseudo bit line contact layers to form through holes in the substrate; and forming bit line contact layers that fill the through holes in the substrate and are electrically connected to the active areas.Type: GrantFiled: September 28, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Er-Xuan Ping, Zhen Zhou, Lingguo Zhang
-
Patent number: 11854535Abstract: Devices and techniques are generally described for machine learning personalization as a service for speech processing applications. In various examples, a first request for machine learning prediction for a first speech processing skill. First skill data schema data may be received that describes content of the first speech processing skill. A first machine learning model for the first speech processing skill may be determined. A first feature definition describing a first aspect of the content may be determined. A second feature definition describing user profile data may be determined. A prediction request may be received from the first speech processing skill. First feature data may be generated according to the first feature definition and second feature data may be generated according to the second feature definition based at least in part on the prediction request.Type: GrantFiled: March 26, 2019Date of Patent: December 26, 2023Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Sihui Zhang, Amber Roy Chowdhury, Hassan Haider Malik, Sanjay Kumar, Uday S. Sandhar, Pawel Matykiewicz, Ming Ma, Anand Vishwanath Suvarnkar
-
Patent number: 11854880Abstract: This application relates to a memory device and a method for manufacturing the same, including: a substrate on which an insulation structure and a plurality of first active structures are formed is provided. The plurality of first active structures are arranged at intervals in the insulation structure. A word line conductive layer is formed on the substrate by a physical vapor deposition process. The word line conductive layer is patterned and etched to obtain a plurality of word line structures arranged in parallel and at intervals and filling slots located between adjacent word line structures. The filling slots comprise first filling slots that expose both parts of top surfaces of the first active structures and parts of the top surface of the insulation structure. Second active structures are formed in the first filling slots, and isolation structures are formed in the first filling slots.Type: GrantFiled: August 25, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Tao Chen
-
Patent number: 11854941Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and covering a cover plate wafer on the first surface of the substrate wafer to seal up the groove so as to form a semiconductor package structure, a gap between the substrate wafer, the semiconductor die stack and the cover plate wafer being not filled with a filler.Type: GrantFiled: July 12, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jie Liu, Zhan Ying
-
Patent number: 11856755Abstract: The present disclosure provides a method for manufacturing a memory, including: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer, and forming a plurality of discrete pseudo bit line layers on the substrate; forming a support layer, the support layer filling areas between the adjacent pseudo bit line layers; removing the pseudo bit line layers to form bit line spaces between adjacent parts of the support layer; forming bit line structures, the bit line structures filling the bit line spaces, and the bit line structures including a bit line conductive layer and a bit line insulating layer sequentially stacked; and removing the support layer, and forming openings between the adjacent bit line structures.Type: GrantFiled: June 30, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jingwen Lu
-
Patent number: 11853152Abstract: A Fail Bit (FB) repair method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on a first FB using a redundant circuit; a bit position of a second FB in each target repair bank is determined, and second repair processing is performed on the second FB; an unrepaired FB in each target repair bank is determined, and candidate repair combinations of the unrepaired FBs and a candidate combination count are determined; and if the candidate combination count is greater than a combination count threshold, a target repair position is determined, and repair processing is performed on the target repair position using a Redundant Word-Line (RWL), the target repair position being a position of an FB that maximally reduces the candidate combination count after repair processing.Type: GrantFiled: August 17, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yui-Lang Chen
-
Patent number: 11853962Abstract: The present application relates to track barcode automatic mounting system and method of an automatic material handling system (AMHS), which system comprises: a running track, at whose position corresponding to an unloading port is provided a barcode mounting region; an overhead hoist transport, installed on the running track, and being moveable along the running track; a locating device, for determining whether the overhead hoist transport has moved to a designated barcode mounting region; a barcode automatic printing and mounting device, disposed on the overhead hoist transport; and a manually operated controller, for sending a movement instruction to the overhead hoist transport to control the overhead hoist transport to move to the designated barcode mounting region, and sending a print confirmation instruction to the barcode automatic printing and mounting device after the overhead hoist transport has moved to the designated barcode mounting region.Type: GrantFiled: November 18, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Tong Lu
-
Patent number: 11854881Abstract: Embodiments of the present application relate to a method for manufacturing a semiconductor structure, includes: forming a contact metal layer on a silicon substrate; performing a plasma treatment process, and forming an oxygen isolation layer on a surface of the contact metal layer; and performing a silicidation reaction process, and converting the contact metal layer into a metal silicide layer.Type: GrantFiled: July 29, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Biao Zhang
-
Patent number: 11854604Abstract: A sense amplifier, a control method of the sense amplifier, and a memory are provided. The sense amplifier includes: a first power input terminal, a second power input terminal, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a first negative-channel metal-oxide semiconductor (NMOS) transistor, a second NMOS transistor, a first positive-channel metal-oxide semiconductor (PMOS) transistor and a second PMOS transistor.Type: GrantFiled: June 30, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Weijie Cheng
-
Patent number: 11854885Abstract: The present disclosure provides a semiconductor structure, a forming method thereof, and a semiconductor device, and relates to the technical field of semiconductor packaging processes. The method includes: providing a semiconductor substrate; forming an oxide layer on a surface of the semiconductor substrate, and etching the oxide layer to form a recess, where a through-silicon via (TSV) is provided in the semiconductor substrate and the oxide layer, and an upper end of the TSV is connected to the recess; depositing a metal layer on a surface of the recess, and forming an opening in the metal layer on a bottom surface of the recess, where the opening is connected to the TSV; and filling a second conductive material into the recess, and forming a hole in the second conductive material above the opening.Type: GrantFiled: April 12, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Chih-Wei Chang
-
Patent number: 11854301Abstract: A person may attempt to gain access to a facility via transaction data, such as images of a hand of the person or other identifying information as acquired by an input device. Possible fraud may be detected by comparing the transaction data with previously stored exclusion data. The exclusion data may include known bad data or synthetic trained data for detecting possible fraud. If the biometric input matches or is similar to the exclusion data, possible fraud is detected and the person is prompted for additional data. The reply data acquired from the person is compared with the exclusion data to determine if possible fraud is still detected. If so, additional prompts are presented to the person until the reply data provides enough confidence of no fraud or until the transaction is terminated.Type: GrantFiled: April 6, 2023Date of Patent: December 26, 2023Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Manoj Aggarwal, Brad Musick, Gerard Guy Medioni, Rui Zhao, Zhen Han
-
Patent number: 11854915Abstract: The present disclosure provides an electrical test structure, a semiconductor structure and an electrical test method. In the electrical test structure, in a first direction, the electrical test structure includes a first layer, an interconnect hole and a second layer arranged in a stack, and the interconnect hole is in contact with the first layer; the second layer includes a body part and a test part, and the test part is connected to the body part; the interconnect hole is configured as, when an offset distance of the interconnect hole relative to a preset position in a second direction is less than a first preset distance, or an offset distance of the interconnect hole relative to the preset position in a third direction is less than a second preset distance, the interconnect hole is spaced apart from the test part.Type: GrantFiled: November 2, 2021Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Hai Wang
-
Patent number: 11853550Abstract: A system and method for encoding data using a plurality of encoding libraries. Portions of the data are encoded by different encoding libraries, depending on which library provides the greatest compaction for a given portion of the data. This methodology not only provides substantial improvements in data compaction over use of a single data compaction algorithm with the highest average compaction, but provides substantial additional security in that multiple decoding libraries must be used to decode the data. In some embodiments, each portion of data may further be encoded using different sourceblock sizes, providing further security enhancements as decoding requires multiple decoding libraries and knowledge of the sourceblock size used for each portion of the data. In some embodiments, encoding libraries may be randomly or pseudo-randomly rotated to provide additional security.Type: GrantFiled: December 29, 2022Date of Patent: December 26, 2023Assignee: ATOMBEAM TECHNOLOGIES INC.Inventors: Joshua Cooper, Aliasghar Riahi, Mojgan Haddad, Ryan Kourosh Riahi, Razmin Riahi, Charles Yeomans
-
Patent number: 11855032Abstract: The disclosed semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.Type: GrantFiled: June 15, 2020Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Ling-Yi Chuang
-
Patent number: 11855673Abstract: Described herein are radio tray assemblies that include space for a specific radio and its power supply and that additionally provide cooling and power conversion and control functionalities. The disclosed radio tray assemblies are designed to have a form factor compatible with legacy radio systems (e.g., MIDS-LVT) while enabling installation of a new radio system (e.g., MIDS-JTRS). The disclosed radio tray assemblies are configured so that the radio and its power supply are secured to a tray so that the radio and power supply are side-by-side and parallel lengthwise. A cooling module or assembly of the disclosed radio tray assemblies is disposed immediately behind the radio and its power supply and is configured to cool these units using forced air cooling directed lengthwise through the radio and its power supply. A power converter and controller module converts input power into the power required by the radio power supply.Type: GrantFiled: July 28, 2022Date of Patent: December 26, 2023Assignee: L3 TECHNOLOGIES, INC.Inventors: Gregory D. Ostrin, Thomas J. Rock, Gregory A. Smyth
-
Patent number: 11854691Abstract: One embodiment provides a method including receiving natural language speech from a user. The method includes automatically converting the natural language speech into a text format and executing a function corresponding to the function portion of the natural language speech. The method includes translating data returned by executing the function into natural language, wherein the translating includes modifying sensitive information within the data returned by (i) changing a selected audible output device and output volume to prevent the at least one unauthorized user from hearing the data returned and (ii) modifying the data returned. The method also includes outputting the natural language via an audible output device. Other aspects are described and claimed.Type: GrantFiled: June 20, 2022Date of Patent: December 26, 2023Assignee: TELETRACKING TECHNOLOGIES, INC.Inventors: Deepak Bhurani, Manoj Kamavarapu, Sagar Cheekati, Shane Torsell, Clinton Wadley
-
Patent number: 11852800Abstract: Increasing transparency of one or more micro-displays. A method includes attaching a transparent cover to at least a portion of a semiconductor wafer. The at least a portion of the semiconductor wafer includes the one or more micro-displays. The one or more micro-displays include one or more active silicon areas. The method further includes, after the transparent cover has been attached to the at least a portion of the semiconductor wafer, removing silicon between one or more of the active silicon areas, causing the one or more micro-displays to have a transparency of at least 50%.Type: GrantFiled: November 15, 2022Date of Patent: December 26, 2023Assignee: L3HARRIS TECHNOLOGIES, INC.Inventors: Jacob Becker, Jon Burnsed