Patents Assigned to TECHNOLOGIES INC.
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Publication number: 20220307908Abstract: The present invention provides a semiconductor device comprising a storage chip and a temperature detection module for detecting a temperature of the storage chip. When the temperature detected by the temperature detection module reaches a set threshold, the storage chip is activated. The present invention utilizes the temperature detection module to detect the temperature of the storage chip so as to provide a reference for the activation and operation of the storage chip, avoiding the activation and operation of the storage chip under low temperatures, shortening write time, and improving the stability of the storage chip write; the temperature detection module has a simple circuit structure and is easy for implementation, with a small occupied area, exerting no influence on the active area of the storage chip.Type: ApplicationFiled: November 11, 2020Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shuliang NING
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Publication number: 20220310460Abstract: A test method for an alignment error includes: providing a substrate, wherein a first conductive layer and a second conductive layer are arranged on the substrate at intervals, and the first conductive layer and the second conductive layer are arranged in a first direction; acquiring a first distance; acquiring a first resistance of the first conductive layer and a second resistance of the second conductive layer; acquiring an actual distance between the first conductive layer and the second conductive layer according to the first distance, the first resistance, and the second resistance; and acquiring a value of the alignment error between the first conductive layer and the second conductive layer based on the actual distance and a standard distance between the first conductive layer and the second conductive layer.Type: ApplicationFiled: October 27, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Xiaodong LUO
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Publication number: 20220310458Abstract: The present application relates to a semiconductor device and a manufacturing method thereof. The method includes: obtaining a substrate, a first device region, a second device region and a high-k gate dielectric layer film being formed on the substrate; forming, on the substrate, a barrier layer structure covering the high-k gate dielectric layer film at the second device region; forming a covering layer film including a first metal element on the substrate; and diffusing the first metal element in the covering layer film towards the high-k gate dielectric layer film at the first device region using an annealing process, the barrier layer structure preventing the first metal element from being diffused towards the high-k gate dielectric layer film at the second device region; wherein the first device region and the second device region have opposite conduction types.Type: ApplicationFiled: May 25, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jie BAI, Kang YOU
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Publication number: 20220310392Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate, a bottom protecting wall being formed in the substrate; forming a mask layer on the substrate; forming a groove in the mask layer, a non-zero angle existing between a sidewall of the groove and a sidewall of the bottom protecting wall, and the bottom of the groove extending into the substrate; and forming a top protecting wall in the groove, the top protecting wall being in direct contact with the bottom protecting wall.Type: ApplicationFiled: February 7, 2022Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Mengmeng WANG, Hsin-Pin HUANG, Qiang ZHANG
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Publication number: 20220310414Abstract: A wet processing device includes a first channel, a nozzle, a second channel, and a sensor. The nozzle includes a spout communicated with the first channel. Negative pressure is formed in the second channel. The second channel includes an opening, the spout is located in the second channel, and the opening is located below the spout. The sensor is configured to detect whether there is liquid in the nozzle.Type: ApplicationFiled: April 16, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Feng ZHANG
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Publication number: 20220310782Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate, the surface of the semiconductor substrate having a plurality of active areas and shallow trench isolation areas arranged in a first direction; etching the active areas and the shallow trench isolation areas in a direction perpendicular to the first direction to form first recesses and second recesses; covering the surfaces of the first recesses and the second recesses with an adhesive layer and a metal layer; and secondarily etching the metal layer and the adhesive layer in the direction perpendicular to the first direction to form a contact hole, the depth of the adhesive layer in the contact hole being defined as H2.Type: ApplicationFiled: April 12, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Junchao ZHANG, Cheng Yeh HSU
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Publication number: 20220308458Abstract: A photolithography device includes: a fixed slot, configured to install and fix the light source; a sensing module, configured to sense the distance information between the light source and the fixed slot; a prompt module, configured to send prompt information according to the distance information; and a determination module, configured to determine the installation status of the light source according to the prompt information.Type: ApplicationFiled: April 16, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Xueyu LIANG
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Publication number: 20220310426Abstract: A manufacturing-process detection method and apparatus for a wafer, a medium and an electronic device are provided. The detection method includes: acquiring a first end time of manufacturing of the wafer in a first manufacturing chamber; acquiring a first start time of manufacturing of the wafer in a second manufacturing chamber, wherein the first manufacturing chamber and the second manufacturing chamber are manufacturing chambers in a same equipment; and detecting an actual waiting time of the wafer between the manufacturing chambers according to the first end time and the first start time.Type: ApplicationFiled: June 16, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Panpan QIN, Wenying SHI
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Publication number: 20220310607Abstract: A method for manufacturing a mask structure includes: patterning a sacrificial layer and a second dielectric layer, so as to form pattern structures each including a first pattern and a second pattern, and a width of a lower portion of the pattern structures is less than a width of a upper portion of the pattern structures; forming an initial mask pattern on sidewalls of each of the plurality of pattern structures; filling a first filling layer between adjacent initial mask patterns located on the sidewalls of different pattern structures; removing the second patterns and the initial mask pattern located on sidewalls of each of the plurality of second patterns; removing the first filling layer and the first patterns, so as to form first mask patterns; and forming second mask patterns on the first mask patterns.Type: ApplicationFiled: September 23, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Qiang WAN, JUN XIA, Penghui XU, Tao LIU, Sen LI, Kangshu ZHAN
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Publication number: 20220305201Abstract: The invention discloses a miniature closed-loop artificial pancreas system, comprising: infusion unit configured to deliver drugs; program unit comprising input end and output end, and the input end comprises a plurality of electrically connective regions for receiving signals of analyte data in the body fluid, after the output end is electrically connected to the infusion unit, according to the received signals of analyte data in the body fluid, the program unit controls whether the infusion unit delivers drugs; an infusion cannula with conductive area, the infusion cannula is the drug infusion channel; and a plurality of electrodes for detecting analyte data in body fluid, the electrode comprising conductive-area electrode and cannula-wall electrode, and one or more cannula-wall electrodes being located on/in the wall of the infusion cannula. It takes only one insertion to perform both analyte detection and drug infusion.Type: ApplicationFiled: December 31, 2019Publication date: September 29, 2022Applicant: MEDTRUM TECHNOLOGIES INC.Inventor: Cuijun YANG
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Publication number: 20220307934Abstract: A built-in calibration sub-system of, or an auxiliary device to be used with, a normally closed water supply control system of the type that uses a single pressure sensor and a pressure decay versus time measurement to make volumetric flow determinations for water supply control purposes, including leak detection and flood risk mitigation is provided. The present disclosure provides a system that uses an auxiliary electrically actuated valve and an orifice to cause a controlled flow of water to discharge from a plumbing network over a pre-determined pressure range such that the normally closed water supply control system's microprocessor can calculate the calibration factor it needs that relates change in pressure over time to volumetric flow rate. Methods of calibration and testing of the leak detection feature of a normally closed water supply control system are also provided.Type: ApplicationFiled: March 25, 2022Publication date: September 29, 2022Applicant: FLOODPROTECH TECHNOLOGIES INC.Inventors: Kirk A. DOBBS, Len SHANKLAND
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Publication number: 20220310614Abstract: The embodiments of the present disclosure belong to the technical field of semiconductor manufacturing, and relate to a semiconductor structure and a method for manufacturing a semiconductor structure. Each of a plurality of storage structures in the semiconductor structure includes a plurality of capacitor structures stacked in a direction perpendicular to a substrate, each of the plurality of capacitor structures includes a bottom plate and an top plate which are arranged opposite to each other, and a first dielectric layer located between the bottom plate and the top plate, and the bottom plate and the top plate are both parallel to the substrate, all bottom plates in each of the plurality of storage structures are electrically connected, and all top plates in each of the plurality of storage structures are electrically connected; the bottom plate and the top plate extend in a plane parallel to the substrate.Type: ApplicationFiled: January 13, 2022Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Kangshu ZHAN, JUN XIA, Qiang WAN, Tao LIU, Sen LI
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Publication number: 20220307140Abstract: A film layer curing apparatus includes: a support platform, configured to carry a substrate having a film layer on the substrate surface; and a light source component located above the support platform, the light source component including a light source array being arranged toward the support platform and covering the light outgoing surface of the entire film layer by projection of the light source array, the light source array including multiple point light sources evenly distributed on the light outgoing surface, light emitted by the light source array being able to uniformly irradiate the entire film layer so as to improve the thickness distribution uniformity of the film layer after curing.Type: ApplicationFiled: May 8, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Tiancheng WU
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Publication number: 20220310462Abstract: Disclosed is a semiconductor structure, disposed on a substrate surface of the die, and the die comprises an internal chip circuit. The semiconductor structure comprises: a first guard ring, annularly disposed around the internal chip circuit and configured to suppress a mechanical damage to the die; and a second guard ring, annularly disposed around the internal chip circuit and configured to suppress the mechanical damage and to monitor the magnitude of the mechanical damage. The second guard ring comprises a plurality of first structures and a plurality of second structures, and the first structure and the second structure have different mechanical strengths and different resistivities.Type: ApplicationFiled: March 18, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: ChihCheng LIU
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Publication number: 20220310152Abstract: A word line driving circuit includes a driving circuit and a control circuit. The control circuit includes a control sub-circuit, a first switching sub-circuit and a second switching sub-circuit. The first switching sub-circuit is provided with: a control terminal electrically connected with the control sub-circuit, a first terminal electrically connected with a first power supply voltage, and a second terminal electrically connected with a third input terminal of the driving circuit. The second switching sub-circuit is provided with: a control terminal electrically connected with the control sub-circuit, a first terminal electrically connected with a second power supply voltage, and a second terminal electrically connected with the third input terminal of the driving circuit. The second power supply voltage is greater than a ground voltage.Type: ApplicationFiled: February 19, 2022Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Cheng-Jer YANG
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Publication number: 20220310625Abstract: The present invention relates to a semiconductor structure and its forming method, and a memory and its forming method. The semiconductor structure includes a substrate, a vertical transistor on the substrate, and a bit line connected to the bottom of the vertical transistor and disposed between the bottom of the vertical transistor and the substrate. The vertical transistor in such a semiconductor structure has a relatively small plane dimension.Type: ApplicationFiled: November 11, 2020Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yiming ZHU, Erxuan PING
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Publication number: 20220310623Abstract: A method for preparing a capacitor contact structure of a memory device includes providing a substrate, forming a plurality of bit line structures arranged in parallel and at intervals on the substrate, and the bit line structures extending along a first direction; forming conducting layer structures between adjacent bit line structures, upper surfaces of which are lower than upper surfaces of the bit line structures; forming sacrificial layers on the conducting layer structures; forming a plurality of isolation trenches arranged in parallel and at intervals in the sacrificial layer, the isolation trenches extend along a second direction, and the second direction intersects the first direction; forming isolation dielectric layers in the isolation trenches; and removing the sacrificial layer based on the bit line structure and the isolation dielectric layer to form grooves between adjacent bit line structures and between adjacent isolation dielectric layers, the grooves expose the conducting layer structures.Type: ApplicationFiled: August 26, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Zhongming LIU, SHIJIE BAI, Longyang CHEN
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Publication number: 20220310391Abstract: A method for manufacturing the mask structure includes: forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer; forming a first mask pattern on sidewalls of the first pattern structure; forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of the first buffer layer; removing the first pattern structure; and removing a remaining protective layer.Type: ApplicationFiled: October 22, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yexiao YU, Zhongming LIU, Jia FANG
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Publication number: 20220310618Abstract: The present application relates to the technical field of semiconductor manufacturing, in particular to a method for forming a film layer with uniform thickness distribution and a semiconductor structure. The method for forming a film layer with uniform thickness distribution comprises: providing a substrate, a non-flat surface for forming a film layer being provided in the substrate; forming a first sub-layer on the non-flat surface at a first temperature by an in-situ steam generation process; and, forming a second sub-layer on a surface of the first sub-layer at a second temperature by an in-situ steam generation process, the film layer at least comprising the first sub-layer and the second sub-layer, the second temperature being higher than the first temperature.Type: ApplicationFiled: March 1, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Tao CHEN, Cheng Yeh HSU, WenHao Hsieh
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Publication number: 20220310187Abstract: A redundant circuit assigning method includes: executing a first test item to obtain first test data including position data of fail bits acquired during execution of the first test item; determining a first redundant circuit assigning result according to the first test data, where the first redundant circuit assigning result includes a number of assigned local redundant circuits and their corresponding position data; executing a second test item to obtain second test data including position data of fail bits acquired during execution of the second test item; and determining a second redundant circuit assigning result according to the first test data and the second test data, when the fail bits acquired during the execution of the second test item include one or more fail bits beyond a repair range of the assigned local redundant circuits and assigned global redundant circuits and when assignable local redundant circuits have been assigned.Type: ApplicationFiled: January 21, 2022Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: YUI-LANG CHEN