Abstract: A semiconductor structure includes: a substrate and a dielectric layer, in which the substrate has a front surface and a back surface which are oppositely arranged, and the dielectric layer is formed on the front surface; a connecting hole, penetrating through the substrate and extending to the dielectric layer; an insulating layer, located on the surface of the inner wall of the connecting hole; and a connecting structure, comprising a first barrier layer, a second barrier layer and a conductive structure, in which the first barrier layer is located on a surface of the insulating layer, the second barrier layer is located between the first barrier layer and the conductive structure, and an air gap exists between the second barrier layer and the first barrier layer.

Abstract: A memory includes: a substrate, having a plurality of active regions arranged in an array and a plurality of word lines extending in a first direction, the active regions being inclined at a preset angle to the word lines, the active region having at least one access transistor; a plurality of bit lines, extending in a second direction perpendicular to the first direction; magnetic tunnel junctions, one end of the magnetic tunnel junction is electrically connected to one of bit lines and another end of the magnetic tunnel junction is electrically connected to two access transistors, the two access transistors electrically connected to the magnetic tunnel junction being located in two adjacent active regions, respectively.

Abstract: The present application provides a temperature calibration method for a semiconductor machine, including following steps: providing at least one temperature calibration sheet, the temperature calibration sheet comprising a transistor having a voltage-temperature characteristic curve corresponding to a set current; placing the temperature calibration sheet in a measurement region of the semiconductor machine; energizing the temperature calibration sheet at an energizing current being the same as the set current, and measuring a voltage of the transistor; and, obtaining a temperature of the transistor according to the voltage-temperature characteristic curve of the transistor by using the voltage as a known parameter, the temperature being a temperature of the measurement region of the semiconductor machine. The accuracy of temperature calibration is greatly improved, the performance of the semiconductor machine and the yield of the semiconductor manufacturing process are also improved.

Abstract: A method includes receiving treatment data pertaining to a user capable of using a treatment device to perform a treatment plan and receiving activity data pertaining to the user while the user engages in at least one activity. The method also includes generating treatment information using the treatment data and the activity data and writing to an associated memory, for access by a healthcare professional, the treatment information. The method also includes modifying at least one aspect of the treatment plan in response to receiving, from the healthcare professional, treatment plan input including at least one modification to the at least one aspect of the treatment plan.

Abstract: A semiconductor structure includes: a base including a substrate and a dielectric layer, herein the substrate having a front surface and a back surface that are oppositely arranged, and the dielectric layer is located on the front surface; a connecting hole penetrating the substrate and extending to the dielectric layer; a connecting structure, located in the connecting hole; and an insulating structure, located between the connecting structure and the inner wall of the connecting hole. The insulating structure, the inner wall of the connecting hole, and the connecting structure define an air gap.

Abstract: A temperature calibration sheet includes a main body and a plurality of test keys arranged in the main body. The test keys have voltage-temperature characteristic curves corresponding to a set current. Temperatures of the test keys are obtained by detecting voltages of the test keys. The temperature calibration sheet can simulate a state of a wafer, sidewalls of the test keys are not exposed to the air, and the state of the temperature calibration sheet arranged on a semiconductor machine is the same as that of the wafer arranged on the semiconductor machine, such that the temperature of the temperature calibration sheet can truly reflect the temperature of the wafer when arranged on the semiconductor machine, and the temperature of the semiconductor machine can be calibrated accurately.

Abstract: A read/write method includes: applying a read command to a memory device, the read command pointing to address information, reading to-be-read data from a storage cell corresponding to the address information to which the read command points, and if an error occurs in the to-be-read data, storing the address information to which the read command points in a preset storage space. The read/write operation is not performed on the address information stored in the preset storage space when the user executes the read or write operation on the memory device, which avoids a data error or data loss and greatly improves the reliability and prolongs the service life of the memory device.

Abstract: An alignment mark count acquiring method includes: acquiring a first time at which an exposure machine performs exposure of a first wafer, and acquiring a second time at which the exposure machine performs alignment of a second wafer; acquiring a first buffer time between the second time and the first time when the first time is less than the second time; determining a target alignment mark count of the second wafer according to the exposure parameters of the first wafer and the corresponding relationship when the first buffer time is greater than a preset value, wherein the corresponding relationship is the relationship between the exposure parameters and the alignment mark counts, and the corresponding relationship is used to make the first buffer time to be less than or equal to the preset value; and outputting the target alignment mark count.

Abstract: An anti-fuse unit structure includes a substrate, an anti-fuse device, and a select transistor. The anti-fuse device is formed in the substrate and comprises a first gate structure, a first source doped region, and a first drain doped region, wherein the first gate structure is electrically connected to the first drain doped region. The select transistor is formed in the substrate and matched with the anti-fuse device, and comprises a second gate structure, a second source doped region and a second drain doped region, wherein the second drain doped region is electrically connected to the first source doped region.

Abstract: The present application relates to a wafer processing device and a wafer processing method. The wafer processing device includes: a spraying unit configured to spray a photoresist-removing solution to remove a photoresist; and a heating unit mounted to the spraying unit and configured to heat the photoresist-removing solution to a preset temperature. According to the wafer processing device and wafer processing method of the present application, the photoresist-removing solution is heated to a preset temperature, so that the photoresist-removing solution dissolves the photoresist more rapidly and thoroughly. Therefore, the photoresist may be removed from a surface of the wafer more thoroughly, and further a yield of the wafer is increased.

Abstract: A critical dimension measurement mark structure includes a target area and a first pattern area located in the target area. The first pattern area and the target area are located on different horizontal planes. The first pattern area includes a first measurement part and a second measurement part which have different line widths, and the first measurement part and the second measurement part form an asymmetric open continuous pattern.

Abstract: A model parameter test structure for a transistor includes: a substrate, having a first conductivity type, a plurality of isolation structures being provided in the substrate and the isolation structures being used to isolate different doped regions; a first test device, formed in the substrate and configured to obtain characteristic parameters of a source side of the transistor; and a second test device, formed in the substrate and configured to obtain characteristic parameters of a drain side of the transistor; wherein a structure of the first test device is different from a structure of the second test device.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming an initial trench in the substrate; forming a sacrificial layer, the sacrificial layer including a first portion and a second portion, the first portion filling the initial trench and the second portion covering an upper surface of the substrate and an upper surface of the first portion; forming a division groove in the second portion, to pattern the second portion into a sacrificial pattern, the sacrificial pattern being arranged corresponding to the first portion; forming a filling layer in the division groove, the filling layer filling the division groove; removing the sacrificial pattern and the first portion, to form a word line trench; and forming a buried gate word line in the word line trench.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate and a plurality of discrete bit line structures located on the substrate, the bit line structure having a metal layer therein, a top surface of the metal layer being lower than a top surface of the bit line structure; forming a first isolation film filled between the adjacent bit line structures, a top surface of the first isolation film being higher than the top surface of the metal layer and lower than the top surface of the bit line structure; forming a first dielectric film on the top and sidewalls of the bit line structure and on the top surface of the first isolation film; and etching to remove the first dielectric film on the top of the bit line structures and the top surface of the first isolation film to form a first dielectric layer, and etching to remove the first isolation film exposed by the first dielectric layer to form a first isolation layer exactly below the first dielectric layer.

Abstract: The present disclosure provides a wafer sample analysis method and device. The method is applied to a secondary-ion-mass spectroscope (Sims) and includes: providing a wafer sample, the wafer sample at least including a slope configured to expose a substrate, a first protective layer and a first doped layer on a same surface, the first protective layer being formed on the substrate, and the first doped layer being formed on the first protective layer; and acquiring and analyzing a slope image of the slope to obtain a doping depth and a doping concentration of elements in the wafer sample in the slope image.

Abstract: A preparation method of a capacitor array structure includes: providing a capacitor substrate which comprises an upper electrode filling layer; forming an insulating layer on a side face of the upper electrode filling layer; forming an upper electrode metal layer on an upper surface of the upper electrode filling layer; forming a planarization layer on an outer surface of the upper electrode metal layer; and forming a first conductor which is connected to the upper electrode metal layer after running through the planarization layer as well as a second conductor which is connected to a lower circuit after running through the planarization layer, the insulating layer and an isolation layer.

Abstract: A method for forming a capacitor array structure includes the following steps: providing a substrate, a capacitor contact being exposed on a surface of the substrate, and the substrate including an array region and a peripheral region; forming a bottom supporting layer covering the substrate and the capacitor contact, the bottom supporting layer having a gap therein; forming a filling layer filling the gap and covering the capacitor contact and the surface of the bottom supporting layer, a thickness of the filling layer located at the peripheral region being larger than that of the filling layer located at the array region; forming supporting layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate; forming a capacitor hole.

Abstract: A mask layout method includes: forming, on a mask, chip patterns arranged in an array, a scribe line being formed between every two adjacent chip patterns, the scribe line being used to provide mark patterns thereon, the mark patterns comprising at least first mark patterns; acquiring a set number of divided units of the first mark patterns; providing the set number of divided units in sequence on the scribe line so that the first mark patterns do not cover other mark patterns; and providing, on the scribe line, first mark pattern elements to replace at least two adjacent divided units, the first mark pattern elements completely overlapping patterns formed by the at least two adjacent divided units.

Abstract: Disclosed are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, including a substrate and a dielectric layer, where the substrate includes a front surface and a back surface that are opposite to each other; the dielectric layer is formed on the front surface; the base is provided with a via hole; the via hole penetrates the substrate from the back surface of the substrate and extends to the dielectric layer; an insulating layer, located on an inner wall surface of the via hole; and a conductive structure, where the conductive structure includes a first conductive layer and a second conductive layer connected to each other; the first conductive layer is close to a bottom of the via hole, and the second conductive layer is close to a top of the via hole.

Abstract: A machine station file processing method includes: monitoring operation of a file system of a machine station server and acquiring a transaction file generated by the operation, the transaction file comprising transaction data; converting a format of the transaction data according to preset warehousing rules to generate model-layer data; and sending, to a data warehouse server, the model-layer data and a data analysis request, the data analysis request is used to instruct the data warehouse server to acquire application-layer data according to the model-layer data.